A Current Balanced Logic Buffer based Time-To-Digital Converter with Improved Resolution

Authors

  • Pooja Saxena

Keywords:

time-to-digital converter, time stamping, tapped delay line, current balanced logic, delay lock loop, high energy physics (HEP)

Abstract

This paper presents design and implementation of TDC based on time stamping using current balanced logic CBL buffer in 0 35 m CMOS technology The CBL logic buffer provides smaller delay compared to widely used current starved inverter allowing better resolution in a given technology node The CBL buffer based tapped delay line TDL provides accurate reference timing signals for time stamping through latching their status by event signal The time stamping is designed with dynamic range of 40 s and allows tunable resolution with minimum value of 136 ps by varying CBL delay using off-chip reference voltage Across process voltage temperature PVT variations by stabilizing the CBL delay with the help of delay lock loop DLL the attained resolution is 174 ps This TDC is designed to work in two modes- Time Interval TI measurement mode and common stop multi-hit mode to enhance scope of its utilization

How to Cite

Pooja Saxena. (2015). A Current Balanced Logic Buffer based Time-To-Digital Converter with Improved Resolution. Global Journals of Research in Engineering, 15(F4), 11–17. Retrieved from https://engineeringresearch.org/index.php/GJRE/article/view/1301

A Current Balanced Logic Buffer based Time-To-Digital Converter with Improved Resolution

Published

2015-03-15