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\title{A Current Balanced Logic Buffer based Time-To-Digital Converter with Improved Resolution}
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             \author[1]{Pooja  Saxena}

             \affil[1]{  Homi Bhabha National Institute}

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\date{\small \em Received: 4 February 2015 Accepted: 2 March 2015 Published: 15 March 2015}

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\begin{abstract}
        


This paper presents design and implementation of TDC based on time stamping using current balanced logic (CBL) buffer in 0.35 ?m CMOS technology. The CBL logic buffer provides smaller delay compared to widely used current starved inverter, allowing better resolution in a given technology node. The CBL buffer based tapped delay line (TDL) provides accurate reference timing signals for time stamping through latching their status by event signal. The time stamping is designed with dynamic range of 40 ?s and allows tunable resolution with minimum value of 136 ps by varying CBL delay using off-chip reference voltage. Across process voltage & temperature (PVT) variations, by stabilizing the CBL delay with the help of delay lock loop (DLL), the attained resolution is 174 ps. This TDC is designed to work in two modes- Time Interval (TI) measurement mode and common stop multi-hit mode to enhance scope of its utilization.

\end{abstract}


\keywords{time-to-digital converter, time stamping, tapped delay line, current balanced logic, delay lock loop, high energy physics (HEP).}

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\let\tabcellsep& 	 	 		 
\section[{Introduction}]{Introduction}\par
ime-to-digital converter (TDC) is an important functional unit for accurate time interval (TI) measurement between 'start' and 'stop' events in HEP experiments. In India based Neutrino Observatory (INO) HEP experiment, TI measurement between 'start' \& 'stop' with resolution better than 200 ps is required. Also, multiple start transitions along with width of 'start' signal need to be measured over dynamic range (DR) of 32 ?s. The measurement of multiple start transitions is used to find delayed events. The width of 'start' signal is used for 'time over threshold' \hyperref[b0]{[1]} implementation required in time walk error correction.\par
To cater to above stated requirements in 0.35 ?m CMOS technology, this paper presents a design \& implementation of TDC based on time stamping \hyperref[b1]{[2]}. This TDC stamps arrival time of events with respect to reference clock (100 MHz) using tapped delay line (TDL) combined with a counter. The number of bits in counter is chosen as 12 to achieve time stamping range of (212-1) ×10 ns = 40.95 ?s, which is higher than the required value of 32 ?s. The resolution of TDC depends on the least delay provided by the delay element, used to realize TDL. In the chosen technology, the least achievable delay in current starved inverter based delay element is \textasciitilde  400 ps, which does not fulfill the required resolution of TI measurement. To achieve resolution better than that attainable in a given technology in the earlier reported TDCs \hyperref[b2]{[3]}  \hyperref[b3]{[4]}, a delay interpolation technique has been used. This technique requires multiple DLLs to interpolate the delay of current starved inverter, leading to large power \& area consumption. In second approach used in \hyperref[b4]{[5]}, a high speed differential delay element has been used, which requires high static current (\textasciitilde 1 mA) to provide small delays. In this design, with constrained requirement of low power due to millions of detector channels, a high speed voltage controlled buffer based on Current Balanced Logic (CBL) \hyperref[b5]{[6]}[7] is designed. It has advantages of small area (4 transistors), identical edge transition delays, wide delay regulation range (\textasciitilde 1.6 ns) and propagation delay (136 ps), which is smaller than that (\textasciitilde  400 ps) in current starved inverter. Also, the CBL delay element has less design complexity as both transition delays are controlled by single bias voltage whereas in current starved inverter two bias voltages are needed to control the rising and falling edge delays.\par
This paper is organized in three sections. Section-II discusses the design and implementation of time stamping based TDC ASIC. The simulation results in support of performance validation of this design are discussed in section-III. Finally, conclusions are drawn in section-IV. 
\section[{II. dc asic Architecture}]{II. dc asic Architecture}\par
The TDC ASIC is designed to work in two measurement modes: 8-channel TI and 4-channel multihit, by stamping the arrival time of events with respect to a reference clock (100 MHz). It consists of following blocks: control logic block, Pre-processor, CBL based TDL along with DLL, transition detector, 12-bit coarse counter, 17 fine \& 17 coarse registers, memory \& its interface logic and readout interface, as shown in Fig. \hyperref[fig_1]{1(a)}.\par
The logic control block enables a 'clock' for TDL and counter on an external 'event reset' signal to initialize the time stamping. Subsequently, it opens a 'dynamic range (DR) window' of duration 40 ?s to enable the pre-processor block. It processes the inputs 'start', 'stop' and 'trigger' events for stamping their arrival times within DR window in both the modes of TDC. In TI mode, each pre-processor block is dedicated for two channels of TDC. In each channel, arrival times (T1 and T2) of 'start' and 'stop' is stamped independently with respect to clock as shown in Fig. \hyperref[fig_1]{1(b}). The difference of their time stamped values is used to measure TI between them.\par
In multi-hit mode, each preprocessor block is dedicated to the single channel of TDC to separate out the four transitions (1, 2, 3, \& 4) in the 'start' signal. The arrival time of each transition is stamped independently with respect to clock. The difference in time stamped values corresponding to first two transitions is used to measure pulse width of 'start' signal. The stamped times of third and fourth transitions are used to find delayed events. The time of trigger is also stamped with respect to clock to find its associated events within DR window. The design aspects of time stamping are given in subsection A.\par
The time stamped data from each channel of TDC is transferred to inbuilt memory. The data transfer is controlled by the logic control block. It issues a read command to the memory; to read the channels only if stop and trigger is present in the window in TI and multihit modes respectively. In their absence, the channel data is discarded. The TDC channel data from memory is transferred to external interface by using either Serial Peripheral Interface (SPI) or parallel interface based read-out logic. The resolution of TDC is defined by the CBL delay, which is stabilized across PVT variations by the control voltage provided by DLL. The DLL and time stamping blocks are designed in close proximity of each other to minimize the process induced CBL delay mismatch in both the blocks. Along with DLL, an optional provision for CBL delay tuning by using off-chip reference voltage is designed. To find the tuned CBL delay value, a calibration scheme is designed. The design and implementation of CBL delay stabilization, tuning, \& calibration is discussed in sub-section B. The occurrence time of event (start/stop/trigger) is stamped in two parts-coarse and fine (Fig. \hyperref[fig_1]{1(b)}). The coarse time, corresponding to the elapsed full cycles of clock till the occurrence of event, is measured by using 12-bit counter. The fine (fractional) time within one clock period (T ref =10 ns) covered by an event is measured by using TDL.\par
The TDL is realized by a chain of cascaded 'N' number of CBL buffers each with delay 'T d ', which defines the resolution of time stamping. For stabilized CBL delay of 174 ps, 58 number of CBL buffers are required for TDL to cover a range of one clock period T ref = 10 ns, by using equation \hyperref[b0]{(1)}. However, in this design to allow the least tunable CBL delay of 136 ps at V dd = 3.6 V as resolution for time stamping, 74 CBL delay elements are used in TDL. It provides 74 uniform delayed replicas of applied 'clock' signal with TI of T d . These delayed clocks are shared among 17-fine registers, 16 for measurement channels (4 channels in multi-hit or 8-channels in TI) and one for trigger channel to measure fine time of events.T ref = N×T d (1)\par
The fine time of each event is measured by finding the elapsed number of delayed clocks till its occurrence. To determine this number, two architectures of fine time measurement are analyzed. In the first, the delayed clocks sample and latch the status of event signal in fine register as shown in Fig. \hyperref[fig_2]{2(a)}. The first logic '0' to '1' transition count in the thermometer code of fine register gives fine count (N f ). For correct fine count, it is desired to disable the sampling of 'event' status before next clock cycle. However, due to uncontrolled processing delays, the first few bits of fine register in the thermometer code are overwritten before sampling gets disabled. This issue of code overwrite is avoided in second architecture of fine time measurement. Here, the 'event signal samples and latches the status of 74-delayed clocks in fine register as shown in Fig. \hyperref[fig_2]{2(b)}. The first logic '1' to '0' transition count in the fine register non-thermometer code gives the fine count (N f ). This transition count is detected by using a transition detector based on magnitude comparison between two consecutive bits of fine register. Further, the encoder converts the 74-bit fine count to 7-bit binary value to reduce the number of bits of fine count. This 7-bit fine count (N f ) multiplied with CBL delay 'T d ' ( ? 136 p s) evaluates the fine time of event with respect to the rising edge of clock cycle in which it lies. The elapsed full clock cycles before arrival of event is measured by coarse time. In coarse time measurement of event, it samples and latches the status of free running counter. While sampling if event occurs during switching of counter, the latched count will be incorrect due to setup time violation or dead zone in the coarse register. Also, the coarse and fine counts need to be synchronized to avoid an error of one coarse count. To address these issues, a dual edge synchronizer based on the dual synchronization scheme \hyperref[b7]{[8]} is designed as shown in Fig. \hyperref[fig_3]{3(a)}. This synchronizer samples \& latches the status of counter when it is in idle state, thereby avoids timing violations in coarse register. The latched count of elapsed clock periods has one extra count, which is irrespective of event position (I, II \& III) within a clock period as shown in Fig. \hyperref[fig_3]{3(b)}. This is carried out by synchronizing the 'event' signal to both the rising and falling edges of clock, resulting in the generation of latched signals Q 1 and Q 2 respectively. A MUX selects the signals 'Q 1 ' or 'Q 2 ' as per the 'event' position to obtain the 'latch\textunderscore event' at falling edge of clock in next cycle. It samples and latches the count status 'N c '.\par
The measured coarse count (N c ) and fine count (N f ) are used in calculation of arrival time (T) of event with respect to clock by using equation \hyperref[b1]{(2)}. The considered value of coarse count is 'N c -2' as two counts are subtracted-one due to synchronization scheme and other due to addition of fine time with coarse time (Fig. \hyperref[fig_1]{1}(b)). T=(N c ?2)×T ref +N f ×T d (2) 
\section[{b) CBL delay stabilization \& Tuning}]{b) CBL delay stabilization \& Tuning}\par
The CBL delay in time stamping block is stabilized across PVT variations by the control voltage obtained from DLL as shown in Fig. \hyperref[fig_4]{4}. The DLL is enabled by applying a rising edge of 'start DLL' signal in the 'start control circuit'. It provides a clock (clock\textunderscore TDL) for reference TDL, whose initial delay is set to minimum value (4.09 ns) by pre-setting the capacitor voltage through 'preset switch' to avoid false locking in DLL. The feedback loop consisting of phase detector, charge pump and filter capacitor, locks the TDL delay to the half clock period (5 ns) of reference clock (complementary clock\textunderscore TDL) across PVT variations in acquisition time of 124 cycles of clock. The attained stable voltage across filter capacitor is used to stabilize the CBL delay to 174 ps across PVT variations.\par
The half clock period locking in DLL is designed to reduce its acquisition time. To further reduce the acquisition time, the initial delay of reference TDL can be fixed nearer to the target value by 'preset switch'. Thus, the present architecture achieves better performance as compared to earlier reported architecture \hyperref[b8]{[9]} \hyperref[b9]{[10]}, where the TDL delay with load of fine register channels is locked to reference clock period in long acquisition time. Along with CBL delay stabilization, an option for its delay tuning using off-chip reference voltage is designed. It is selected by resetting the D flip-flops used in start control circuit. It turns on the 'preset switch' as well as disables DLL, so that the filter capacitor is charged to the off-chip reference voltage.\par
The voltage across filter capacitor is applied to TDL (time stamping block) for delay stabilization or tuning through bias circuit \hyperref[b7]{[8]}. The purpose of bias circuit utilization is to avoid the loading of long delay lines on filter capacitor (C) by charge sharing with the parasitic capacitances of TDL.\par
The tuned value of CBL delay is determined by measuring on-chip generated time intervals of 10 ns and 5 ns in between 'calstart' and 'calstop' signals (Fig. \hyperref[fig_1]{1(a)}). These time intervals are generated by using reference clock. The calibration mode is selected by 1-bit 'cal' signal. The CBL delay 'T d ' is given by the difference of measured time intervals by using equation \hyperref[b2]{(3)}, where N f1 and N f2 are the counts of fine registers corresponding to 10 ns and 5 ns time intervals respectively. The calibrated CBL delay is used to calculate the final stamped time of event using equation (  {\ref 2}).  
\section[{Simulation Result}]{Simulation Result}\par
The post layout performance of CBL delay element is verified by using Spectre simulator across design process corners. The CBL delay characteristic for both rising and falling edge transitions is shown in Fig.  {\ref 5} The ripple of 40 ?V in the DLL control voltage after attaining the locked state also causes variation in tapped delays. This is evaluated by simulating the extracted netlist of TDL with DLL for 1000 number of clock cycles. The standard deviation of delay variation is shown in Fig. \hyperref[fig_6]{7}(b) with maximum value of 0.14 ps at the end of delay line.\par
To find the variations in tapped delays due to device component noise, noise coupling through parasitics and variation in layout drawing, the extracted netlist of TDL is accurately simulated by Spectre simulator with transistor noise models. The maximum delay variation is 17 ps as shown in Fig. \hyperref[fig_6]{7(c}) and its RMS value is 10 ps.\par
The RMS quantization error for the resolution of 174 ps is evaluated by: 174 ps / ?12 = 50.28 ps. The total theoretical RMS error in TI measurement, considering above evaluated RMS delay variations and quantization error, is calculated as 55.02 ps.   
\section[{Conclusions}]{Conclusions}\par
The TDC based on CBL logic achieves improved resolution in 0.35?m CMOS technology. The designed architecture of time stamping allows tunable resolution with least value of 136 ps. Across PVT variations; the attained resolution is 174 ps by stabilizing the CBL delay with the help of DLL. The CBL buffer provides identical rising and falling edge delays, which enables to control both delays with a single DLL feedback loop which in turn reduces design complexity. The designed TDC can be utilized in TI and Multi-hit operating modes with dynamic range of 40 ?s. The multi-hit operating mode features pulse width measurement of 'start' signal with duration better than \textasciitilde 5 ns, which is independent of used clock frequency. Also, it enables measurement of delayed events over range of 40 ?s. This design is successfully tested for its linearity as well as robustness across design process corners. The theoretical RMS error in time interval measurement is calculated as 55.02 ps.\begin{figure}[htbp]
\noindent\textbf{2015}\includegraphics[]{image-2.png}
\caption{\label{fig_0}T © 2015}\end{figure}
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\noindent\textbf{1}\includegraphics[]{image-3.png}
\caption{\label{fig_1}Fig. 1 :A}\end{figure}
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\noindent\textbf{2}\includegraphics[]{image-4.png}
\caption{\label{fig_2}Fig. 2 :}\end{figure}
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\noindent\textbf{3}\includegraphics[]{image-5.png}
\caption{\label{fig_3}Fig. 3 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{4}\includegraphics[]{image-6.png}
\caption{\label{fig_4}Fig. 4 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{56}\includegraphics[]{image-7.png}
\caption{\label{fig_5}Fig. 5 :Fig. 6 :}\end{figure}
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\noindent\textbf{7}\includegraphics[]{image-8.png}
\caption{\label{fig_6}Fig. 7 :}\end{figure}
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\noindent\textbf{89}\includegraphics[]{image-9.png}
\caption{\label{fig_7}Fig. 8 :Fig. 9 :}\end{figure}
 			\footnote{© 2015 Global Journals Inc. (US)} 		 		\backmatter  			 
\subsection[{Global Journals Inc. (US) Guidelines Handbook 2015}]{Global Journals Inc. (US) Guidelines Handbook 2015}\par
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