Abstract

High peak-to-average power ratio (PAPR) of the transmitted signal is a major drawback of orthogonal frequency division multiplexing (OFDM). Selected mapping (SLM) technique is one of the promising PAPR reduction techniques for OFDM. In the SLM technique, statistically independent data blocks are generated from an OFDM data block using a set of phase sequences and one with the lowest PAPR is chosen and transmitted. In this paper, we propose an SLM technique which gives sizable reduction of nearly 2dB. The paper elaborates the hardware implementation of the generated block using FPGA. The test benches and the RTL schematic are generated.