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\title{Designing of Automatic Traffic Light Controller in Roads and Railways Transport System for Controlling Purpose}
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             \author[1]{Mr. Prashant  Kumar}

             \affil[1]{  Amity University Uttar Pradesh, Lucknow}

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\date{\small \em Received: 8 December 2012 Accepted: 1 January 2013 Published: 15 January 2013}

\maketitle


\begin{abstract}
        


With the Traffic Light only the chances of roadside accident and human error based Railway Accidents are reduced to minimal amount these days. With the increasing number of roads and trains, the requirement for accuracy based controlling the traffic lights is increasing day by day in future generation. This paper is an attempt to introduce the reader into the world of Digital Electronics and Hardware Description Language based device. Traffic Light Controller plays a very important role in the Roads and Railways based Automatic Controlling System.  The designing of Automatic Traffic Light Controller System for Roads and Railways Purpose through control the traffic of city, maintain the tracks andpublic places. The Automatic Traffic Light Controller in Railway System placed at Four Line Central Based Server which control the Railway Traffic through the Automatic Designing based System. This Traffic Light Controller plays the operation in Roads Service through controlling the Roads in the concept of Digital Electronics. This project is based on the construction and working of this Automatic Traffic Light Controller Chip Based System. This paper gives the Virtual Operation as Simulation and Integrated Circuit Performance which has to be designed in Hardware Description Language by using the concept of Digital Electronics. 

\end{abstract}


\keywords{introduction, controlling system in roads, controlling system in railways, concept of digital electronics, using software in this controlling system, }

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\textcolor{GJBlue}{\footnotesize \\ Artificial Intelligence formulated this projection for compatibility purposes from the original article published at Global Journals. However, this technology is currently in beta. \emph{Therefore, kindly ignore odd layouts, missed formulae, text, tables, or figures.}}
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\let\tabcellsep& 	 	 		 \par
Controlling System in Railways-The maintaining of Traffic Light Controller System in Railways is based on the Central HUB Server which controls the four zonal direction of Railways. There are certain problems and for solving the problem of hazard and human accidental case in railways, I have to design the Restart and Clock Control System which comes from the concept of Sequential Circuit. This Restart and Clock System creates the following action when hazard and human accidental problem has started and then this system will manually restart that zone direction of Traffic Light Controller System.\par
The Indian Railways System is the busy and hazards creating system. This hazard shows the  0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 0 1 0 0 1 0 1 0 0 1 1 1 0 0 0 1 0 0 1 0 0 1 1 0 1 1 1 0 1 0 0 0 1 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 0 0 1 0 0 1 0 0 1 1 1 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 1 0 0 0 0 1 1 0 0 1 0 0 1 0 0 1 0 0 0 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 1 0 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 0 1 0 0 0 1 0 1 0 0 1 1 1 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 0 0 1 0 0 1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 world's largest supplier of programmable logic devices and being free. This application also enable the helps you design, test and debugging integrated circuits. 
\section[{? Abbreviations used in Truth}]{? Abbreviations used in Truth}\par
If you ever tried to design and implement any kind of electronic circuits, digital concepts, connecting cables, LED's and chips, as soon as we know that pretty soon all you end up with a big and confusing pile of small colour cables. There are some applications which available that we shall help to keep things in perspective and respective manner for transposing the logic and circuit to your screen. This will benefit in a lot of ways as soon that we can forget about implementing the bread boards malfunctions or looking for hours through burned (forgotten) chip. Xilinx ISE simply takes this idea to the next level (several levels above in VLSI Design). We will have access to hundreds of industrial standard chips, from the standard AND or NOT gates that it can get all the way to the more complex ones (including multiplexers, counters etc.). If we do not find that what you need you will be able to design it and use it just as another chip from the library.\par
After the Design and Logic Circuit Phase, we can test our design by changing inputs and checking the results in this software. This will take few time in each circuit has to be completely compiled and completed before the test can be done. As we might have already concluded, this is not program for the beginner. The user interface has although clean and full of nice buttons but cannot hide the complexity of the underlying process. We shall most probably need the user manual of this software. This is very advanced program in HDL Language to be used by engineers at production and industrial level in VLSI Design by designing the chips in IC Fabrication.\par
One word of advice that however, we save our work frequently. Xilinx will crash repeatedly when compiling our work in HDL Language. It will not recognize our save files and it will not be able to read our data. If we try to save everything in a simple folder in the root of our disk, no characters besides letters, no special words and no spaces as soon as possible. I have always managed to get my work back but I surely would not like to have to work with this application on a daily basis. editor, digital circuit design and simulator. DSCH is always used to validate the architecture of the logic circuit and digital design before the microelectronics design is started. DSCH also provides a user-friendly environment for hierarchical logic and digital design, fast simulation with delay and logic analysis, which allows the design and compilation of complex logic structures. DSCH also features the symbols of logic gates, models and assembly support for 8051 and other Micro Controllers. Designers can create the logic circuits for interfacing with these controllers and verify software programs using DSCH. Highlights 1. User-friendly environment for rapid design of logic circuits.\par
2. Supports hierarchical logic design. 5. Current and power consumption analysis.\par
6. Generates a VERILOG description of the schematic for layout conversion. \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-2.png}
\caption{\label{fig_0}Traffic}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-3.png}
\caption{\label{fig_1}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{1}\includegraphics[]{image-4.png}
\caption{\label{fig_2}Advantages 1 .}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{3}\includegraphics[]{image-5.png}
\caption{\label{fig_3}3 .}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{7}\includegraphics[]{image-6.png}
\caption{\label{fig_4}7 .}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-7.png}
\caption{\label{figure7}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-8.png}
\caption{\label{figure8}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-9.png}
\caption{\label{figure9}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-10.png}
\caption{\label{figure10}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-11.png}
\caption{\label{figure11}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-12.png}
\caption{\label{figure12}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{} \par 
\begin{longtable}{P{0.85\textwidth}}
language is enabling for producing the valuable\\
information as location and other things in Railways\\
System. This Controller can be used at Parking System,\\
Vehicle Controlling Purpose, Educational Projects and\\
other Public Places.\\
Controlling System in Roads-This controlling\\
system is to design the Traffic Light Controller with the\\
concepts of Four Directions Roads System. It controls\\
the main city points as North, South, East and West\\
Direction. This is the Automatic System Based Traffic\\
Light Controller System.\\
Introduction\\
raffic Light plays the most important role in our life\\
while dealing with huge traffic and increasing\\
population. It also plays to develop the Automatic\\
Controller System which enable for Error Free\\
Controlling System. This traffic light controller enables\\
for designing as Digital Designing Concepts by\\
programming in VHDL and Verilog HDL as Hardware\\
Description Language. This paper gives me the new\\
way for developing the Automatic System Based Traffic\\
Light Controller and marketing as launching this product\\
in India. This Controller System enable for Roads and\\
Railways Project with the Automatic Controller System.\\
The Traffic Light Controller based on this designing\end{longtable} \par
 
\caption{\label{tab_0}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{A} \par 
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\multicolumn{2}{l}{NR: NORTH RED.}\tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \\
\multicolumn{2}{l}{WG: WEST GREEN.}\tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \\
\multicolumn{2}{l}{WY: WEST YELLOW.}\tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \\
WR: WEST RED.\tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \\
\multicolumn{2}{l}{SG: SOUTH GREEN.}\tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \\
\multicolumn{2}{l}{SY: SOUTH YELLOW.}\tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \end{longtable} \par
  {\small\itshape [Note: SR: SOUTH RED. EG: EAST GREEN. EY: EAST YELLOW. ER: EAST RED. XIII Issue XV Version I 3 ( )]} 
\caption{\label{tab_1}Table A}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{} \par 
\begin{longtable}{P{0.04047619047619047\textwidth}P{0.013492063492063491\textwidth}P{0.026984126984126982\textwidth}P{0.026984126984126982\textwidth}P{0.026984126984126982\textwidth}P{0.4992063492063492\textwidth}P{0.026984126984126982\textwidth}P{0.026984126984126982\textwidth}P{0.026984126984126982\textwidth}P{0.026984126984126982\textwidth}P{0.026984126984126982\textwidth}P{0.026984126984126982\textwidth}P{0.026984126984126982\textwidth}P{0.026984126984126982\textwidth}}
\tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \multicolumn{4}{l}{When Rst= '1' in All Zone Direction}\tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \\
A B\tabcellsep C\tabcellsep NG\tabcellsep NY\tabcellsep NR\tabcellsep WG\tabcellsep WY\tabcellsep WR\tabcellsep SG\tabcellsep SY\tabcellsep SR\tabcellsep EG\tabcellsep EY\tabcellsep ER\end{longtable} \par
 
\caption{\label{tab_4}}\end{figure}
 			\footnote{© 2013 Global Journals Inc. (US)} 		 		\backmatter  			 
\subsection[{This page is intentionally left blank}]{This page is intentionally left blank}			 			  				\begin{bibitemlist}{1}
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\end{document}
