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\title{An Adder with Novel PMOS and NMOS for Ultra Low Power Applications in Deep Submicron Technology}
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\begin{document}

             \author[1]{Ch. Ashok  Babu}

             \author[2]{J.V.R.  Ravindra}

             \author[3]{K. Lal  Kishore}

             \affil[1]{  Swami Vivekananda Institute of Technology}

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\date{\small \em Received: 10 December 2012 Accepted: 1 January 2013 Published: 15 January 2013}

\maketitle


\begin{abstract}
        


Power has become a burning issue in modern VLSI design, as the technology advances especially below 45nm technology, Leakage power become more problem apart of the dynamic power. This paper presents a full adder with novel PMOS and NMOS which consume less power compare to conventional full adder and DTMOS full adder, this paper shows different types of adders and their power consumption, area and delay. All the experiments have been carried out using cadence virtuoso design lay out editor which shows power consumption of different types of adders[1-2].

\end{abstract}


\keywords{average power, leakage power, delay, DTMOS, PDP.}

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\textcolor{GJBlue}{\footnotesize \\ Artificial Intelligence formulated this projection for compatibility purposes from the original article published at Global Journals. However, this technology is currently in beta. \emph{Therefore, kindly ignore odd layouts, missed formulae, text, tables, or figures.}}
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\let\tabcellsep& 	 	 		 
\section[{Introduction}]{Introduction}\par
he adder is one of the most critical components of a central processing unit. The object of the adders not only adding of bits but also involves in address calculation, subtraction, division and multiplication, the adders are critical components to determine the speed, delay and power of the overall system, low power adders are always preferable. Due to the popularity of portable electronic products low power system has attracted more attention in recent years, an system on chip (SOC) design can contain more and more components that lead to a higher power density. This makes power dissipation reach the limits of what packaging, cooling or other infrastructure can support, reducing the power consumption not only can enhance battery life but also can avoid the overheating problem which would increase the difficulty of packaging or cooling. Therefore the consideration of power consumption in complex SOCs has become a big challenge to designers, moreover in modern VLSI designs \hyperref[b2]{[3]}\hyperref[b3]{[4]}\hyperref[b4]{[5]}.\par
Lowering power is one of the greatest challenges facing the IC industry Today, temperature profile and battery life requirements for tethered and un tethered systems have made power consumption a primary optimization target for IC industry \hyperref[b1]{[2]}. IC power consumption consists of three basics components: switching power, short circuit power and leakage power \hyperref[b5]{[6]}\hyperref[b6]{[7]}.\par
Dynamic power2 DD L D V f C 2 1 P = (1)\par
Dynamic power is square of supply voltage, therefore by reducing supply voltage we can reduce dynamic power \hyperref[b7]{[8]}.\par
The leakage power is mainly due to sub threshold current and it may be defined as the drain to source current of the transistor operating in the weak inversion region of MOSFET this subthreshold leakage may be defined as in eq \hyperref[b1]{(2)} give s a simple method for estimating the leakage current in a single NMOS transistor \hyperref[b8]{[9]}\hyperref[b9]{[10]}\hyperref[b10]{[11]}.\par
( )? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = t ds t t gs v V V v V I exp 1 exp I 0 s ? (2)\par
V t is the thermal voltage and is given by Q/KT and n is the sub threshold slope coefficient. Generally there are varies leakage reduction techniques based on mode of operation of systems the two operation modes are active mode and stand by mode or idle mode. Most of the leakage power reduction techniques will be based on idle mode \hyperref[b11]{[12]}. SECTION2: gives an overview of the Novel PMOS and NMOS and their simulation results, SECTION3 presents Novel 3 bit full adder and conventional full adder, SECTION 4 describes experimental results of conventional, Novel full adders and DTMOS full adders, SECTION5gives conclusions.\par
II. 
\section[{An Over View of Novel PMOS and NMOS}]{An Over View of Novel PMOS and NMOS}\par
Ultra low power operation plays a major role in designing of CMOS circuits in subthreshold regime, for any digital or analog design the basic components are PMOS and NMOS devices, the power consumption of this basic elements determine the overall power of the system. In this section we provide Novel PMOS and NMOS, simulations have been carried out in cadence design frame work to verify the functionality of the  
\section[{A Conventional CMOS Adder}]{A Conventional CMOS Adder}\par
The 28 transistor full adder is the pioneer traditional adder circuit, the schematic of this adder is shown. This adder cell is built using equal number of NFET and PFET transistors, the MOS logic can be realized using equations \hyperref[b0]{[1]}.Carry: AB+BC+AC (2) SUM: ABC+(A+B+C)C\textbf{(3)}\par
The conventional full adder consumes more power compared to Novel full adder, both conventional and Novel full adders are simulated and their average power is calculated \hyperref[b13]{[14]}.   
\section[{Simulation Results and Analysis}]{Simulation Results and Analysis}\par
An investigation has been carried out for calculating average power, static power of conventional full adder and the Novel full adder and compared their powers at 45nm technology using virtuoso design environment.\par
A novel CMOS adder may have an overhead area, but it consumes less power \hyperref[b14]{[15]}.     
\section[{Conclusions}]{Conclusions}\par
The performance of many large circuits are strongly dependent on the performance of the full adder circuits that have been used. An attempt has been made to design 84T novel full adder with low power consumption. In this paper we have simulated conventional full adder and Novel full adder and calculated average power. As mentioned earlier as the technology advances apart of dynamic power, there will be a equal part of leakage power, therefore a Novel full adder will suitable for low power design.\begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-2.png}
\caption{\label{fig_0}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{3}\includegraphics[]{image-3.png}
\caption{\label{fig_1}Figure 3 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{4}\includegraphics[]{image-4.png}
\caption{\label{fig_2}Figure 4 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{1} \par 
\begin{longtable}{P{0.12405405405405406\textwidth}P{0.3308108108108108\textwidth}P{0.2710810810810811\textwidth}P{0.12405405405405406\textwidth}}
\tabcellsep \multicolumn{2}{l}{Voltage Is 0.6v}\tabcellsep \\
Parameter\tabcellsep Full Adder With Novel PMOS \& NMOS\tabcellsep Conventional CMOS full adder\tabcellsep DTCMOS full adder\\
Avg. Power\tabcellsep 97.23nw\tabcellsep 105.8nw\tabcellsep 243nw\\
Delay\tabcellsep 150ps\tabcellsep 580ps\tabcellsep 291ps\\
PDP\tabcellsep 1.456×10-17\tabcellsep \multicolumn{2}{l}{61×10-15 7.07×10-17}\end{longtable} \par
 
\caption{\label{tab_0}Table 1 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{2} \par 
\begin{longtable}{P{0.43858447488584473\textwidth}P{0.21735159817351596\textwidth}P{0.19406392694063926\textwidth}}
\multicolumn{3}{l}{Conventional CMOS Full Adder Versus Novel Full Adder}\\
\multicolumn{3}{l}{at 45nm and Supply Voltage Is 1.1v}\\
Parameter\tabcellsep Full Adder With Novel PMOS \& NMOS\tabcellsep Conventional CMOS full adder\\
Avg. power\tabcellsep 0.43µw\tabcellsep 1.88µw\\
Delay\tabcellsep 72ps\tabcellsep 43ps\\
PDP\tabcellsep 3.152×10 -17\tabcellsep 8.084×10 -17\end{longtable} \par
 
\caption{\label{tab_1}Table 2 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{3} \par 
\begin{longtable}{P{0.34517766497461927\textwidth}P{0.2934010152284264\textwidth}P{0.2114213197969543\textwidth}}
\multicolumn{3}{l}{Adder and Conventional Full Adder with Supply Voltage}\\
\tabcellsep \multicolumn{2}{l}{of 1.1v @180nm}\\
Parameter\tabcellsep Full Adder With Novel PMOS \& NMOS\tabcellsep Conventional CMOS full adder\\
Avg. power\tabcellsep 69.49µw\tabcellsep 32.8µw\\
Delay\tabcellsep 217ps\tabcellsep 166ps\\
PDP\tabcellsep 15×10 15\tabcellsep 5.45×10 15\end{longtable} \par
 
\caption{\label{tab_2}Table 3 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{4} \par 
\begin{longtable}{P{0.4106741573033708\textwidth}P{0.21647940074906366\textwidth}P{0.13370786516853933\textwidth}P{0.08913857677902622\textwidth}}
\multicolumn{4}{l}{Adder, DTCMOS Full Adder and Conventional Full}\\
\tabcellsep \multicolumn{2}{l}{Adder at 45nm with 0.6v}\tabcellsep \\
Parameter\tabcellsep Full Adder With Novel PMOS \& NMOS\tabcellsep Conventional CMOS full adder\tabcellsep DTCMOS full adder\\
Static power\tabcellsep \tabcellsep \tabcellsep \\
when all inputs are at\tabcellsep 9.159pw\tabcellsep 8.688pw\tabcellsep 109.4nw\\
0.6v\tabcellsep \tabcellsep \tabcellsep \\
Static power\tabcellsep \tabcellsep \tabcellsep \\
when all inputs are at\tabcellsep 14pw\tabcellsep 8.756pw\tabcellsep 78nw\\
0v\tabcellsep \tabcellsep \tabcellsep \end{longtable} \par
 
\caption{\label{tab_3}Table 4 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{5} \par 
\begin{longtable}{P{0.5122767857142857\textwidth}P{0.1783482142857143\textwidth}P{0.159375\textwidth}}
\multicolumn{3}{l}{Adder and Conventional Full Adder at 45nm With1.1v}\\
Parameter\tabcellsep Full Adder With Novel PMOS \& NMOS\tabcellsep Conventional CMOS full adder\\
Static power when\tabcellsep \tabcellsep \\
all inputs are at\tabcellsep 44.6pw\tabcellsep 30.97pw\\
0.6v\tabcellsep \tabcellsep \\
Static power when all inputs are at 0v\tabcellsep 52.18pw\tabcellsep 28.76pw\end{longtable} \par
 
\caption{\label{tab_4}Table 5 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{6} \par 
\begin{longtable}{P{0.522787610619469\textwidth}P{0.17300884955752213\textwidth}P{0.15420353982300886\textwidth}}
\multicolumn{3}{l}{Adder, And Conventional Full Adder At 180nm With1.8v}\\
Parameter\tabcellsep Full Adder With Novel PMOS \& NMOS\tabcellsep Conventional CMOS full adder\\
Static power when\tabcellsep \tabcellsep \\
all inputs are at\tabcellsep 30.97pw\tabcellsep 69.25pw\\
1.8v\tabcellsep \tabcellsep \\
Static power when all inputs are at 0v\tabcellsep 590pw\tabcellsep 97.5pw\\
V.\tabcellsep \tabcellsep \end{longtable} \par
 
\caption{\label{tab_5}Table 6 :}\end{figure}
 			\footnote{© 2013 Global Journals Inc. (US) ( )} 			\footnote{© 2013 Global Journals Inc. (US) ( ) F} 		 		\backmatter  			  				\begin{bibitemlist}{1}
\bibitem[Blotti et al. ()]{b14}\label{b14} 	 		‘A Comparison of Some Circuit Schemes for Semi-Reversible Adiabatic Logic’.  		 			A Blotti 		,  		 			. S Di Pascoli 		,  		 			R Saletti 		.  	 	 		\textit{International Journal of Electronics}  		2002. 89  (2)  p. .  	 
\bibitem[Navi et al. ()]{b6}\label{b6} 	 		‘A High-Speed Hybrid Full Adder’.  		 			R K Navi 		,  		 			Md Reza Saatchi 		,  		 			O Daei 		.  	 	 		\textit{European Journal of Scientific Research}  		2009. 26  (1)  p. .  	 
\bibitem[Zhuang and Wu ()]{b5}\label{b5} 	 		‘A New Design of the CMOS Full Adder’.  		 			N Zhuang 		,  		 			H Wu 		.  	 	 		\textit{IEEE Journal of Solid-state Circuits}  		1992. 27  (5)  p. .  	 
\bibitem[Shalem et al.]{b8}\label{b8} 	 		\textit{A Novel Low Power Energy Recovery Full Adder Cell},  		 			R Shalem 		,  		 			E John 		,  		 			L K John 		.  		 	 	 (publisher unknown) 
\bibitem[Manish Kumar1 et al. ()]{b0}\label{b0} 	 		‘An Improved SOI CMOS Technology Based Circuit Technique for Effective Reduction of Standby Subthreshold Leakage’.  		 			Md Manish Kumar1 		,  		 			Anwar Hussain1 		,  		 			K Sajal 		,  		 			Paul2 		.  	 	 		\textit{Circuits and Systems, Scientific Research}  		October 2013, 4. p. .  	 
\bibitem[Goel et al. ()]{b10}\label{b10} 	 		‘Design of robust, energy efficient full adders for deep-submicrometer design using hybrid CMOS logic style’.  		 			S Goel 		,  		 			A Kumar 		,  		 			M A Bayoumi 		.  	 	 		\textit{IEEE Transactions on VLSI Systems}  		2006. 4  (12)  p. .  	 
\bibitem[Blotti et al. ()]{b11}\label{b11} 	 		‘Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library’.  		 			A Blotti 		,  		 			R Castellucci 		,  		 			Saletti 		.  	 	 		\textit{PATMOS}  		2002. p. .  	 
\bibitem[Soudris et al. ()]{b7}\label{b7} 	 		\textit{Designing Low-Power Energy Recovery Adders Based On Pass Transistor Logic},  		 			D Soudris 		,  		 			V Pavlidis 		,  		 			A Thanailakis 		.  		2001. IEEE.  	 
\bibitem[Dhireesha and John ()]{b12}\label{b12} 	 		‘Implementation of Low Power Digital Multipliers Using 10 Transistor Adder Blocks’.  		 			K Dhireesha 		,  		 			John 		.  	 	 		\textit{Journal of Low power Electronics}  		2005.  (3)  p. .  	 
\bibitem[Alioto and Palumbo ()]{b13}\label{b13} 	 		‘Performance Evaluation of Adiabatic Gates’.  		 			M Alioto 		,  		 			G Palumbo 		.  	 	 		\textit{IEEE Trans on Circuits and Systems-I}  		2000. 47  (9)  p. .  	 
\bibitem[Abou-Samra and Guyot (1998)]{b4}\label{b4} 	 		‘Performance/ Complexity Space Exploration: Bulk vs. SOI’.  		 			S J Abou-Samra 		,  		 			A Guyot 		.  	 	 		\textit{Proceedings of the International Workshop on Power and Timing Modelling, Optimization and Simulation, Lyngby},  				 (the International Workshop on Power and Timing Modelling, Optimization and Simulation, Lyngby)  		October 1998. p. .  	 
\bibitem[Cristoloveanu and Reichert (1998)]{b2}\label{b2} 	 		‘Recent Advances in SOI Materials and Device Technologies for High Temperature’.  		 			S Cristoloveanu 		,  		 			G Reichert 		.  	 	 		\textit{Proceedings of High-Temperature Electronic Materials, Devices and Sensors},  				 (High-Temperature Electronic Materials, Devices and SensorsSan Diego)  		22-27 February 1998. p. .  	 
\bibitem[Reedy (1999)]{b3}\label{b3} 	 		‘Single Chip Wireless Systems Using SOI’.  		 			R Reedy 		.  	 	 		\textit{Proceedings of the International SOI Conference},  				 (the International SOI ConferenceSan Diego)  		4-7 October 1999. p. .  	 
\bibitem[Kado ()]{b1}\label{b1} 	 		‘The Potential of Ultrathin-Film SOI Devices for Low-Power and High-Speed Applications’.  		 			Y Kado 		.  	 	 		\textit{IEICE Transactions on Electronics}  		1997.  (3)  p. .  	 
\bibitem[Chew et al. ()]{b9}\label{b9} 	 		\textit{Ultra Low-Power Full-Adder for Biomedical Applications},  		 			E S Chew 		,  		 			M W Phyu 		,  		 			W L Goh 		.  		2009.  	 	 (IEEE pp115-118) 
\end{bibitemlist}
 			 		 	 
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