An Adder with Novel PMOS and NMOS for Ultra Low Power Applications in Deep Submicron Technology
Keywords:
average power, leakage power, delay, DTMOS, PDP
Abstract
Power has become a burning issue in modern VLSI design as the technology advances especially below 45nm technology Leakage power become more problem apart of the dynamic power This paper presents a full adder with novel PMOS and NMOS which consume less power compare to conventional full adder and DTMOS full adder this paper shows different types of adders and their power consumption area and delay All the experiments have been carried out using cadence virtuoso design lay out editor which shows power consumption of different types of adders 1-2
Downloads
- Article PDF
- TEI XML Kaleidoscope (download in zip)* (Beta by AI)
- Lens* NISO JATS XML (Beta by AI)
- HTML Kaleidoscope* (Beta by AI)
- DBK XML Kaleidoscope (download in zip)* (Beta by AI)
- LaTeX pdf Kaleidoscope* (Beta by AI)
- EPUB Kaleidoscope* (Beta by AI)
- MD Kaleidoscope* (Beta by AI)
- FO Kaleidoscope* (Beta by AI)
- BIB Kaleidoscope* (Beta by AI)
- LaTeX Kaleidoscope* (Beta by AI)
How to Cite
Published
2013-10-15
Issue
Section
License
Copyright (c) 2013 Authors and Global Journals Private Limited
This work is licensed under a Creative Commons Attribution 4.0 International License.