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\title{Design of 8-Bit Arithmetic Processor Unit based on Reversible Logic}
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\begin{document}

             \author[1]{  A.Kamaraj}

             \affil[1]{  Mepco Schlenk Engineering College}

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\date{\small \em Received: 8 December 2012 Accepted: 31 December 2012 Published: 15 January 2013}

\maketitle


\begin{abstract}
        


Reversible logic is emerging as an important research area in the recent years due to its ability to reduce the power dissipation, which is the main requirement in low power digital design. Energy dissipation is proportional to the number of bits lost during computation. The reversible circuits do not lose information and can generate unique outputs from specified inputs and vice versa. It has application in diverse fields such as low power CMOS design, optical information processing, cryptography, quantum computation and nanotechnology. This paper proposes a reversible design of an 8 -bit arithmetic processor. The architecture of the processor has been proposed, in which, each block is realized using reversible logic gates. The important blocks of the processor are control unit, arithmetic and logical unit and register file. Each module has been coded using Verilog then simulated using Modelsim and prototyped in Xilinx-Spartan 3E. 

\end{abstract}


\keywords{reversible logic, reversible gate, FPGA, xilinx.}

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\let\tabcellsep& 	 	 		 
\section[{I. INTRODUCTION}]{I. INTRODUCTION}\par
n modern VLSI system, power dissipation is very high due to rapid switching of internal signals. Landauer showed that the circuits designed using irreversible elements dissipate heat due to the loss of information bits \hyperref[b0]{[1]}. It is proved that the loss of every bit of information results in dissipation of KT*log2 Joule of heat energy where K is the Boltzmann constant and T is the temperature at which the operation is performed.\par
Bennett showed that this heat dissipation due to information loss can be avoided if the circuit is designed using reversible logic gates \hyperref[b0]{[1]}. A gate is considered to be reversible only if each and every input has a unique output assignment. Hence there is a one to one mapping between the input and output vectors. A reversible logic gate has same number of inputs and outputs. 
\section[{II.}]{II.} 
\section[{BASIC REVERSIBLE GATES}]{BASIC REVERSIBLE GATES}\par
There exist many reversible gates in the literature. Among them 2*2 Feynman gate, 3*3 Fredkin gate, 3*3 Toffoli gate and 3*3 Peres gate are the most referred. The detailed cost of a reversible gate depends on any particular realization of quantum logic \hyperref[b1]{[2]}. Generally, the cost is calculated as a total sum of 2*2 quantum primitives used. The cost of Toffoli gate is exactly the same as the cost of Fredkin gate and is 5. The only cheapest quantum realization of a complete (universal) 3*3 reversible gate is Peres gate and its cost is 4.     I3 I2 I1 I0 Operation 0 0 0 0 Clear 0 0 0 1 A+B 0 0 1 0 A-B 0 0 1 1 A*B 0 1 0 0 A++ 0 1 0 1 A-- 0 1 1 0 Left Shift 0 1 1 1 Right Shift 1 0 0 0 Or 1 0 0 1 And 1 0 1 0 Not 1 0 1 1 Xor 1 1 0 0 Nor 1 1 0 1 Nand 1 1 1 0 Xnor 1 1 1 1 Preset\par
The 8-bit reversible adder/subtractor has been designed using Peres gates and Feynman gates \hyperref[b2]{[3]}. HNG gates and Peres gates are used in the design of the 8-bit reversible multiplier \hyperref[b5]{[6]}.The left and right shifter blocks are designed using reversible multiplexers. 
\section[{b) Register File}]{b) Register File}\par
The register file includes 16 registers and two 4 to 16 decoders as shown in the Figure  {\ref .}6. The two select signals 'load' and 'enable' are used for loading data into and reading value of data from the individual registers of the register file respectively. The 4 to 16 decoder is designed using reversible Fredkin gates \hyperref[b3]{[4]}.     ? ALU result registers are also controlled buffer register used to store the result of the ALU operation. ? The Data Bus Buffer is another controlled buffer register that takes input from memory module. It is directly connected to the data bus.\par
IV. 
\section[{SIMULATION RESULTS}]{SIMULATION RESULTS}\par
All the blocks are modelled using VERILOG. The functional verification of the codes is analysed using ModelSim-Altera 6.4a (Quartus II 9.0) Starter Edition and synthesised using Xilinx ISE Design Suite 13.     reversible 8-bit processor has been proposed. Each block of the processor was designed using the basic reversible gates.\par
In future, this design can be extended to any number of bits. This paper provides the circuit level implementation of the reversible processor. Further this design may be extended to transistor implementation which would help in easier analysis of power.\begin{figure}[htbp]
\noindent\textbf{1}\includegraphics[]{image-2.png}
\caption{\label{fig_0}Figure 1 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{2}\includegraphics[]{image-3.png}
\caption{\label{fig_1}Figure 2 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{3}\includegraphics[]{image-4.png}
\caption{\label{fig_2}Figure 3 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{45}\includegraphics[]{image-5.png}
\caption{\label{fig_3}Figure 4 :Figure 5 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{6}\includegraphics[]{image-6.png}
\caption{\label{fig_4}Figure 6 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-7.png}
\caption{\label{fig_5}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{7}\includegraphics[]{image-8.png}
\caption{\label{fig_6}Figure 7 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{8}\includegraphics[]{image-9.png}
\caption{\label{fig_7}Figure 8 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-10.png}
\caption{\label{fig_8}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{9}\includegraphics[]{image-11.png}
\caption{\label{fig_9}Figure 9 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{10}\includegraphics[]{image-12.png}
\caption{\label{fig_10}Figure 10 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{11}\includegraphics[]{image-13.png}
\caption{\label{fig_11}Figure 11 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{12}\includegraphics[]{image-14.png}
\caption{\label{fig_12}Figure 12 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{1} \par 
\begin{longtable}{}
\end{longtable} \par
 
\caption{\label{tab_0}Table 1 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{2} \par 
\begin{longtable}{P{0.16451612903225807\textwidth}P{0.6854838709677419\textwidth}}
Device Id\tabcellsep Device Name\\
000\tabcellsep Accumulator Register\\
001\tabcellsep ALU Result Registers\\
010\tabcellsep Data Bus Buffer Register\end{longtable} \par
 
\caption{\label{tab_1}Table 2 :}\end{figure}
 			\footnote{© 2013 Global Journals Inc. (US)} 			\footnote{Design of 8-Bit Arithmetic Processor Unit Based on Reversible Logic} 			\footnote{© 2013 Global Journals Inc. (US) Design of 8-Bit Arithmetic Processor Unit Based on Reversible Logic} 		 		\backmatter  			  				\begin{bibitemlist}{1}
\bibitem[Design of a Novel Reversible Multiplier Circuit Using HNG Gate in Nanotechnology, Majid Haghparast ()]{b5}\label{b5} 	 		\textit{Design of a Novel Reversible Multiplier Circuit Using HNG Gate in Nanotechnology, Majid Haghparast},  		2008. Tehran, Iran.  		 			Somayyeh Jafarali Jassbi, Islamic Azad University, Tehran, IranKeivan Navi and Omid Hashemipour, Shahid Beheshti University 		 	 
\bibitem[Aradhya et al. (2011)]{b1}\label{b1} 	 		\textit{Design of Control unit for Low Power ALU Using Reversible Logic},  		 			H V Aradhya 		,  		 			Praveen Kumar 		,  		 			B V Muralidhara 		,  		 			KN 		.  		September 2011.  	 
\bibitem[Bennett et al. (1973)]{b0}\label{b0} 	 		\textit{Logical reversibility of computation},  		 			C H Bennett 		,  		 			J Ibm 		,  		 			Research 		,  		 			Development 		.  		November 1973. 17 p. .  	 
\bibitem[Rangaraju et al. (2010)]{b2}\label{b2} 	 		\textit{Low Power Reversible Parallel Binary Adder/Subtractor},  		 			H G Rangaraju 		,  		 			U Venugopal 		,  		 			K N Muralidhara 		,  		 			K Raja 		.  		Sept 2010.  		 			Department of Electronics and Communication Engineering. 		 	 
\bibitem[Mr et al. (2012)]{b4}\label{b4} 	 		 			Mr 		,  		 			Rtu Goyal 		,  		 			Kota; Ms 		,  		 			Vidhi 		,  		 			Sharma 		,  		 			Jaipur 		,  		 			Kota Rtu 		.  		\textit{VHDL Implementation of Reversible Logic Gates},  				May 2012.  	 
\bibitem[Design et al. (2012)]{b3}\label{b3} 	 		\textit{Optimization and Synthesis of Efficient Reversible Logic Binary Decoder, Ravish Aradhya HV},  		 			; Design 		,  		 			R Chinmaye 		,  		 			K N Muralidhara 		,  		 			Bangalore 		.  		May 2012. India.  	 
\end{bibitemlist}
 			 		 	 
\end{document}
