@incollection{,
	
					
					
					05119B9BD008F4FCD18515DC3BCBD490
				,
	author={{A.Kamaraj} and {Mepco Schlenk Engineering College}},
	journal={{Global Journal of Researches in Engineering}},
	journal={{GJRE}}2249-45960975-586110.34257/gjre,
	address={Cambridge, United States},
	publisher={Global Journals Organisation}1310710
}

@book{b0,
	
	
		,
	title={{Logical reversibility of computation}}
		,
	author={{
			CHBennett
		} and {
			JIbm
		} and {
			Research
		} and {
			Development
		}}
		
		
		
		
			,
	year={November 1973}
			17
			
		
	

}

@book{b1,
	
	
		,
	title={{Design of Control unit for Low Power ALU Using Reversible Logic}}
		,
	author={{
			H VAradhya
		} and {
			PraveenKumar
		} and {
			B VMuralidhara
		} and {
			KN
		}}
		
		
		
		
			,
	year={September 2011}
		
	

}

@book{b2,
	
	
		,
	title={{Low Power Reversible Parallel Binary Adder/Subtractor}}
		,
	author={{
			H GRangaraju
		} and {
			UVenugopal
		} and {
			K NMuralidhara
		} and {
			KRaja
		}}
		
		
		
		
			,
	year={Sept 2010}
		
		
			Department of Electronics and Communication Engineering.
		
	

}

@book{b3,
	
	
		,
	title={{Optimization and Synthesis of Efficient Reversible Logic Binary Decoder, Ravish Aradhya HV}}
		,
	author={{
			;Design
		} and {
			RChinmaye
		} and {
			KNMuralidhara
		} and {
			Bangalore
		}}
		
		
		
		
			,
	year={May 2012}
			,
	address={India}
		
	

}

@book{b4,
	
	
		,
	author={{
			Mr
		} and {
			RtuGoyal
		} and {
			Kota; Ms
		} and {
			Vidhi
		} and {
			Sharma
		} and {
			Jaipur
		} and {
			KotaRtu
		}}
		
		
		
		
		
		
		,
	title={{VHDL Implementation of Reversible Logic Gates}}
				
			,
	year={May 2012}
		
	

}

@book{b5,
	
	
		,
	title={{Design of a Novel Reversible Multiplier Circuit Using HNG Gate in Nanotechnology, Majid Haghparast}}
		
			,
	year={2008}
			,
	address={Tehran, Iran}
		
		
			Somayyeh Jafarali Jassbi, Islamic Azad University, Tehran, IranKeivan Navi and Omid Hashemipour, Shahid Beheshti University
		
	

}