# Introduction

ilicon drift detector (SDD) is a device based on the principle of lateral charge transport within the bulk of a fully depleted detector, as proposed by Gatti and Rehak (Reference-1). SDD is essentially detector in which a high resistivity n-type silicon substrate is employed to fabricate p-n junctions on both sides of the substrate. PN junctions on the front side form segmented field shaping cathodes whereas a uniform, p-n junction forms the back-cathode. A reverse bias gradient when applied to the field shaping cathodes together with a constant back-contact voltage creates a potential distribution in the shape of a "Potential Gutter" with the ultimate electron potential energy minimum at the anode. Electron-hole pairs created by passage of ionizing radiation are swept vertically by the parabolic potential along the depth and focused at the local potential minima from where they get drifted along the lateral drift channel towards the anode. The distinguishing feature of the SDD is that its small output (anode) capacitance is independent of its large detector active area.

Thus SDDs are suitable for high resolution (127eV @ 5.9 keV for Mn-K? line; Ketek Vitus SDD) and high count rate (~1x10 6 cps) X-ray spectroscopy applications. These detectors have found wide application in high-energy physics for tracking applications. SDDs have been incorporated in the ALICE detector along the Large Hadron Collider at CERN. This high-resolution capability of SDDs can be further augmented by integrating the input device of the pre-amplifier (JFET) with the detector so as to avoid stray capacitance and microphonism arising due to wire bonding between them. The integration of JFET onto the detector also facilitates better matching between detector and transistor capacitances.

The proto-typing stage fabrication of SDDs at IIT-B has been successfully completed. The first run of the fabrication of the commercial grade SDDs and JFETs has yielded satisfactorily good results. SDDs fabricated at BEL were aimed at both Xray Spectroscopy and position sensing applications. Circular geometry SDDs with in-built low noise JFETs were designed for X-ray Spectroscopy applications. Linear geometry SDDs with on-chip poly-silicon resistors were designed for 1D & 2D position sensing applications. Additionally, high transconductance JFETs were also designed together with various different kinds of SDDs over the 4-inch silicon wafer.


# II.


# Detector Design

This particular version of SDD has an on-chip Poly-Resistor network for biasing the intermediate p+ strips together with an on-chip JFET for first level amplification [Fig. 1(b)]. The anode is in geometry of an annular ring having 50 µm radii with an area of 7.7 x 10 4 µm 2 that fetched an analytical full depletion capacitance of 27 fF for 300 µm thick fully depleted silicon wafer. The total active area of the detector was 2.31 x 10 7 µm 2 . This device had 20 p+ strips with two guard rings encircling its outer perimeter. The first, fifth, tenth, fifteenth, twentieth, and last p+ strips were individually biased whereas the of rest p+ strips got biased by the on-chip resistor. Each poly resistor was designed to present a Fig. 1 (a) : Composite layout of Circular SDD (Pitch-120?m) with in-built JFET.  On the basis of the success of the fabrication effort at IIT-B, the process for the BEL effort was formulated. Formulation of a process for fabrication of SDD and JFET over high resistivity silicon substrate was a significant technological challenge. The process for the fabrication of SDD with integrated JFET was formulated with a view of achieving a high breakdown voltage of >100V, and achieving as low leakage current as possible using the existing fabrication setup at BEL. The process employed at BEL involved all the standard unit processes like oxidation, lithography, etching, and implantation, metallization etc. employed in a bipolar fabrication line. The process parameters have been fine tuned and frozen after a thorough TCAD process simulation study in order to achieve the desired doping profiles for both SDD & JFET. The highest standards of cleanliness and care in planning the unit processes have been maintained to achieve the objectives of low leakage currents together with admissibly high breakdown voltages. Moreover, the process had to be compliant with the technological constraints of the BEL foundry. Additionally, Polysilicon process has been employed for fabrication of on-chip resistor network. The distinguishing feature of this process was the employment of a double-sided processing for back to front alignment of cathode implants. Thus making double sided SDDs a reality, which are far more superior to single sided SDDs. The lithographic quality was again a challenge as the fabrication process involved 14 lithographic steps. definition of the p-type isolation well (Mask-1) within the center of the SDD for housing the embedded JFET. This was followed by an oxide etch step to expose the substrate for boron implantation (E = 80 keV; Dose = 5x10 11 cm -2 ). Subsequent dopant activation and drive-in diffusion of boron species was performed employing the Drive-in cycle as illustrated in the Fig. 4. The simulated doping profile for the p-well implant showed a peak boron concentration of 3.39x10 14 cm -3 for a junction depth of 3.19 ?m and an extracted sheet resistance of 102.705 k?/ . Subsequently, the n-channel within the p-well region was lithographically defined (Mask-2) and phosphorus implantation (E = 150 keV; Dose = 5x10 12 cm -2 ) was performed followed by a drive-in cycle (Fig. 6) to form the n-channel. The simulated doping profile (Fig. 7) for the n-channel showed a peak phosphorus concentration of 3.24x10 16 cm -3 for a junction depth of 2 ?m and an extracted sheet resistance of 2.703 k?/ .

Going ahead from here, the p+ cathodes & p+ guard ring (Mask-3) were lithographically defined on the topsurface whereas the p+ backcontact (Mask-4) was defined on the bottom surface of the wafer employing back to front double-sided alignment lithography. A thin screen-oxide (Fig. 8) was grown over the exposed silicon to create shallow junctions and prevent implantation damage. Boron Implantation (Dose = 1x10 15 cm-2 ; Energy = 80 keV) followed by dopant activation and drive-in (Fig. 9) was performed to create p+ strips, p+ guard ring and p+ back-contact regions. The simulated doping profile showed a peak boron concentration of 2.24x10 18 cm -3 for a junction depth of 1.5 ?m and extracted sheet resistance of 181.93 ?/ . The 5th lithographic (Mask-5) step was performed for definition of p+ type Gate region of the JFET. Boron Implantation (Dose = 1x10 15 cm -2 ; E = 80keV), followed by Drive-in (Fig. 12) was performed to realize the p+ gate region. In the p+ Gate Drive-in case, the analytical value of sheet resistance was 181.93 ?/ , for a junction depth of 1.1 micron and the extracted peak Boron concentration of 1x10 19 cm -3 . Subsequently, n+ Anode, Source & Drain were defined (Mask-6) followed by Phosphorus Implantation (Dose = 1x10 15 cm-2 ; E = 80 keV) forms the n+ regions. The dopant activation and drive-in was performed as per schedule in figure 14. The simulated analytical sheet resistance was 79.3 ?/ , for a characteristic depth of micron and the extracted peak Phosphorus concentration was 1.1x10 20 cm -3 . Following this, oxide openings (Poly-contact: Mask-7) were defined over the p+ strips region to facilitate the poly-silicon layer deposited in the next step to make contact with under-lying p+ region. Poly-Silicon was then deposited and boron implantation was performed to form the poly-resistors having a Sheet Resistance of 138.88 k?/ . After lithographically patterning (Mask-8) the polysilicon layer a short anneal step (Time = 30 minutes; Temperature = 900 o C) was carried out to dopant activation of the species in the poly layer. Proceeding from that, the contact lithography (Mask-9) was performed to open windows through the oxide for making contact with Aluminum metal deposited above for purpose of electrical connection with rest of the electronics. The back-contact was defined (Mask-10) for contact window openings on the back surface of the wafer. Aluminum metallization (Thickness = 1.5 microns) was carried out over the front-surface and lithography was performed (Mask-11) to pattern the metal layer to define the various electrical connections. The back-side was then metalized keeping the frontsurface protected and the metal layer was patterned lithographically (Mask-12) to form the backelectrodes of the SDD. Lastly, Protective glass was deposited over both the front and back-sides followed by lithography (Masks-13 & 14) to open areas over the metal bond pads. The values for sheet resistances, junction depths for various regions have been tabulated in Table -         process. I-V was taken by ramping the voltage at the strip (Cathode-6) from -100 V to 0 V and the anode current was measured through an ammeter (Keithley-2400 SMU used in current sense mode). I-V characteristics were measured for various values of guard-ring voltages (illustrated in Fig. 15). The nature of the I-V curve matched with the nature of I-V curve achieved for the SDDs in IIT case. The embedded lownoise JFET was characterized for its dc performance using the same experimental setup.  
1. ? ? ? ? ? ? (?/ )1![Fig. 1 (b) : Zoomed view of the embedded JFET (JFET-10) showing all mask layers.](image-2.png "Fig. 1 (")
1![Fig. 1 (c) : Photograph of the completely fabricated SDD with in-built JFET. III. Fabrication Of Sdds & Low-Noise Jfets a) Fabrication Objectives](image-3.png "?Fig. 1 (")
23![Fig. 2 : Block Diagrammatic illustration of the process flow.b) Fabrication Process and TCAD SimulationsStarting with a 4-inch n-type, high resistivity (3-5 k?.cm) compensated silicon wafer of <111> orientation, an initial oxide was grown employing the Dry-Wet-Dry regime (Thickness = 0.6µm). The bulk comprising of the wet oxide (t = 0.4µm) was sandwiched between two high quality dry oxide layers (t = 0.1 µm) each. The next step was the lithographic](image-4.png "Fig. 2 :Fig. 3 :")
4![Fig. 4 : Schematic of the Boron Drive-in cycle for p-well.](image-5.png "Fig. 4 :")
56![Fig. 5 : One-Dimensional doping profile of p-well region along depth.](image-6.png "Fig. 5 :Fig. 6 :")
7![Fig. 7 : One-Dimensional doping profile of n-Channel region along depth.](image-7.png "Fig. 7 :")
89![Fig. 8 : Schematic of the Screen Oxidation cycle for p+ Strips.](image-8.png "Fig. 8 :Fig. 9 :")
10![Fig. 10 : One-Dimensional Doping Profile of Annealed Boron Implant for p+ Strips & p+ Guard Ring.](image-9.png "Fig. 10 :")
12![Fig. 12 : Schematic of the Boron Drive-in cycle for p+ Gate.](image-10.png "Fig. 12 :")
13![Fig. 13 : One-Dimensional doping profile of Gate region along the depth.](image-11.png "Fig. 13 :")
14![Fig. 14 : Schematic of the Phosphorus Drive-in cycle for n+ Source, Drain & Anode.](image-12.png "Fig. 14 :p")
1516![Fig. 15 : I-V Characteristics of Circular SDD (Pitch =120?m).](image-13.png "Fig. 15 :Fig. 16 :")
![Voltage [V DS ] (Volts)](image-14.png "")
11
			© 2012 Global Journals Inc. (US)
		
		

			

## Acknowledgements

The author expresses a deep sense of gratitude for Late Dr. S. K. Kataria for his guidance and leadership. The author would like to especially thank Mr. G. P. Srivastava, Mr. Shekhar Basu and Dr. Sinha for their kind support. deviation of less than 30% from that achieved from characterization. The value of noise figure (5.69 nV?Hz) was within the low noise band.

			

			

V GS = 0 Volts V GS = -0.25 Volts V GS = -0.5 Volts V GS = -0.75 Volts

2.0x10 
			
			

				


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