Reducing Hearing Aid Power Consumption Using Truncated-Matrix Multipliers

Authors

  • Thomas L. Hemminger

  • Thomas L. Hemminger

Keywords:

truncated-matrix multipliers, hearing aids, power consumption, coefficient shifting, integer processing

Abstract

The traditional platforms for implementing hearing aid algorithms have been application specific integrated circuits (ASIC) and some general purpose DSP chips. One of the most important issues involved in hearing aid design is power consumption, i.e., battery life. This paper introduces an alternative method for implementing hearing aid algorithms by using truncated-matrix multipliers. These designs can offer a significant reduction in power consumption and chip area. However, the approach can often increase computational error but it can be partially compensated for by introducing a method of coefficient shifting of the filter weights. This latter approach significantly reduces the computational error resulting in improved system performance.

How to Cite

Thomas L. Hemminger, & Thomas L. Hemminger. (2013). Reducing Hearing Aid Power Consumption Using Truncated-Matrix Multipliers. Global Journals of Research in Engineering, 13(8), 1–7. Retrieved from https://engineeringresearch.org/index.php/GJRE/article/view/820

Reducing Hearing Aid Power Consumption Using Truncated-Matrix Multipliers

Published

2013-02-28