@incollection{,
	
					
					
					BC16AF0654B4806D2715FB2F96F99EDD
				,
	author={{Y. SreenivasulaGoud} and {Dr.B.K.Madhavi} and {JNTU, Hyderabad.}},
	journal={{Global Journal of Researches in Engineering}},
	journal={{GJRE}}2249-45960975-586110.34257/gjre,
	address={Cambridge, United States},
	publisher={Global Journals Organisation}1371331
}

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	year={2000}
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	publisher={Kluwer Academic Publishers}
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	address={London}
		
	

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	title={{A Distributed BIST Control Scheme for Complex VLSI Devices}}
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	year={1998}
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	author={{
			SWang
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	author={{
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	title={{A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation}}
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	year={1997}
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@incollection{b11,
	
	
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	title={{Low Power Serial Built-IN Self-Test}}
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	author={{
			AHertwig
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	year={1998}
			
		
	

}

@incollection{b12,
	
	
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	author={{
			SWang
		} and {
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			,
	year={October 1997}
		
	

}

@incollection{b13,
	
	
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	title={{Nanometer technology challenges for test and test equipment}}
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	author={{
			WMNeedham
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	journal={{Computer}}
		
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	title={{Current directions in automatic test-pattern generation}}
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	author={{
			K.-TCheng
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	journal={{Computer}}
		
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			11
			
			,
	year={November 1999}
		
	

}

@incollection{b15,
	
	
		,
	title={{Gate level test generation for sequential circuits}}
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	author={{
			K.-TCheng
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		,
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			4
			
			,
	year={October 1996}
		
	

}

@book{b16,
	
	
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	title={{Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits}}
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	author={{
			MLBushnell
		} and {
			VD
		}}
		
		
			,
	year={2000}
			,
	publisher={Springer Science}
			,
	address={New York, NY}
		
	

}

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		} and {
			C.-WWu
		} and {
			XWen
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	title={{VLSI Test Principles and Architectures: Design for Testability}}
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			,
	publisher={Morgan Kaufmann}
			,
	year={2006}
		
	

}

@incollection{b18,
	
	
		,
	title={{A Case Study of IR-Drop in Structured At-Speed Testing}}
		,
	author={{
			JSaxena
		} and {
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		} and {
			VBJayaram
		} and {
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		} and {
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		} and {
			PSreeprakash
		} and {
			MHachinger
		}}
		
		
		
		
		
		
	
	
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	booktitle={{Proc. Int'l Test Conf}}
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			,
	year={October 2003}
			
		
	

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@incollection{b19,
	
	
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		,
	author={{
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		}}
		
	
	
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			,
	year={September 15, 2004}
		
	

}

@incollection{b20,
	
	
		,
	title={{An Efficient Approach to SOC Wrapper Design, TAM Configuration and Test Scheduling}}
		,
	author={{
			JPouget
		} and {
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		} and {
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		} and {
			MLFlottes
		} and {
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		}}
		
		
		
		
	
	
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	booktitle={{Proc. European Test Workshop}}
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			,
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}

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		,
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			,
	year={April 1993}
			
		
	

}

@incollection{b23,
	
	
		,
	title={{A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation}}
		,
	author={{
			HCheung
		} and {
			SGupta
		}}
		
	
	
		,
	journal={{IEEE Int. Test Conf}}
		
			
			,
	year={October 1996}
		
	

}

@incollection{b24,
	
	
		,
	title={{DS-LFSR: A New BIST TPG for Low Heat Dissipation}}
		,
	author={{
			SWang
		} and {
			SKGupta
		}}
		
	
	
		,
	journal={{IEEE Int. Test Conf}}
		
			
			,
	year={October 1997}
		
	

}

@incollection{b25,
	
	
		,
	title={{Low Power Serial Built-IN Self-Test}}
		,
	author={{
			AHertwigand
		} and {
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		,
	booktitle={{IEEE European Test Workshop}}
				
			,
	year={1998}
			
		
	

}

@incollection{b26,
	
	
		,
	title={{POWERTEST: A Tool for Energy ConciousWeighted Random Pattern Testing}}
		,
	author={{
			KZhang
		} and {
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		} and {
			Bhawmik
		}}
		
		
	
	
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			,
	year={1999}
		
	

}

@incollection{b27,
	
	
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	title={{Low Energy BIST Design: Impact of the LFSR TPG Parameters on the Weighted Switching Activity}}
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	author={{
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		} and {
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		} and {
			SPravos Soudovitch
		} and {
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		} and {
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		} and {
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		} and {
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			,
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}

@incollection{b28,
	
	
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	title={{A Test Vector Inhibiting Technique for Low Energy BIST Design}}
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	author={{
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		} and {
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		} and {
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		} and {
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		}}
		
		
		
	
	
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			,
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}

@incollection{b29,
	
	
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	title={{Low Power BIST by Filtering Non-Detecting Vectors}}
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	author={{
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		} and {
			MSantos
		}}
		
		
		
		
		
		
		
		
	
	
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	journal={{IEEE European Test Workshop}}
		
			,
	year={May 1999}
		
	

}

@book{b30,
	
	
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	year={November 1999}
		
	
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	note={to be presented at IEEE Asian Test Symp.}

}

@incollection{b31,
	
	
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	author={{
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			,
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}

@incollection{b32,
	
	
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	title={{Bench Marking Models of Low Power VLSI Testing Strategies: Current State of the Art 35}}
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	year={1998}
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	publisher={Prentice Hall PTR}
		
	

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@incollection{b34,
	
	
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}

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@incollection{b39,
	
	
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	year={October 1997}
		
	

}

@incollection{b40,
	
	
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			GAlexiou
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@incollection{b41,
	
	
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@incollection{b42,
	
	
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	title={{State assignment for low power dissipation}}
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	journal={{IEEE Transactions on Very Large Scale Integration (VLSI) Systems}}
		
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			,
	year={June 2000}
		
	

}

@incollection{b46,
	
	
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	title={{Saving power by synthesizing gated clocks for sequential circuits}}
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	author={{
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	year={1999}
			
		
	

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	title={{Design of system-on-a-chip test access architectures under place-and-route and power constraints}}
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	author={{
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@incollection{b49,
	
	
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			JBraden
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	year={1997}
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@incollection{b50,
	
	
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@incollection{b51,
	
	
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	booktitle={{IEEE Transactions on Very Large Scale Integration (VLSI) Systems}}
				
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	year={June 1997}
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@incollection{b52,
	
	
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	author={{
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@incollection{b53,
	
	
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	title={{A test pattern generation methodology for low power consumption}}
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	booktitle={{16th IEEE VLSI Test Symposium}}
				
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	year={1998}
			
		
	

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@incollection{b54,
	
	
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	title={{Low power BIST via non-linear hybrid cellular automata}}
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			GSquillero
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	booktitle={{18th IEEE VLSI Test Sym-posium}}
				
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	year={2000}
			
		
	

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@incollection{b55,
	
	
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	title={{A new BIST archi-tecture for low power circuits}}
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	year={1999}
			
		
	

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			MSonza Reorda
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			MViolante
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	year={1999}
			
		
	

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@book{b61,
	
	
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	title={{Principles of Digital Design}}
		,
	author={{
			DDGajski
		}}
		
			,
	year={1997}
			,
	publisher={Prentice-Hall International}
		
	

}

@book{b62,
	
	
		,
	title={{Computers and Intractability: A Guide to the The-ory of NP-Completeness}}
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	author={{
			MRGarey
		} and {
			DSJohnson
		}}
		
		
			,
	year={1979}
			,
	publisher={Morgan Freeman}
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	address={New York}
		
	

}

@book{b63,
	
	
		,
	title={{Algorithms for VLSI Design Automation}}
		,
	author={{
			SHGerez
		}}
		
			,
	year={1999}
			,
	publisher={John Wiley & Sons}
		
	

}

@incollection{b64,
	
	
		,
	title={{Minimized power consumption for scan-based BIST}}
		,
	author={{
			SGerstendorfer
		} and {
			HJWunderlich
		}}
		
	
	
		,
	booktitle={{Proc. IEEE International Test Conference}}
				IEEE International Test Conference
		
			,
	year={1999}
			
		
	

}

@incollection{b65,
	
	
		,
	title={{Minimized power consumption for scan-based BIST}}
		,
	author={{
			SGerstendorfer
		} and {
			HJWunderlich
		}}
		
	
	
		,
	journal={{Journal of Electronic Testing: Theory and Applications (JETTA)}}
		
			16
			3
			
			,
	year={June 2000}
		
	

}

@incollection{b66,
	
	
		,
	title={{Low power testing of VLSI circuits: Problems and solutions}}
		,
	author={{
			PGirard
		}}
	
	
		,
	booktitle={{First International Symposium on Quality of Electronic Design (ISQED)}}
				
			,
	year={2000}
			
		
	

}

@incollection{b67,
	
	
		,
	title={{Circuit partitioning for low power BIST design with minimized peak power consumption}}
		,
	author={{
			PGirard
		} and {
			LGuiller
		} and {
			CLandrault
		} and {
			SPravossoudovitch
		}}
		
		
		
	
	
		,
	booktitle={{8th Asian Test Symposium (ATS99)}}
				
			,
	year={1999}
			
		
	

}

@incollection{b68,
	
	
		,
	title={{A test vector in-hibiting technique for low energy BIST design}}
		,
	author={{
			PGirard
		} and {
			LGuiller
		} and {
			CLandrault
		} and {
			SPravossoudovitch
		}}
		
		
		
	
	
		,
	booktitle={{Proc. 17th IEEE VLSI Test Symposium}}
				17th IEEE VLSI Test Symposium
		
			,
	year={1999}
			
		
	

}

@incollection{b69,
	
	
		,
	title={{A test vector ordering technique for switching activity reduction during test operation}}
		,
	author={{
			PGirard
		} and {
			LGuiller
		} and {
			CLandrault
		} and {
			SPravossoudovitch
		}}
		
		
		
	
	
		,
	booktitle={{9th Great Lakes Symposium on VLSI (GLSVLSI99)}}
				
			,
	year={1999}
			
		
	

}

@incollection{b70,
	
	
		,
	title={{Low power pseudorandom BIST: on selecting the LFSR seed}}
		,
	author={{
			PGirard
		} and {
			LGuiller
		} and {
			CLandrault
		} and {
			SPravossoudovitch
		} and {
			JFigueras
		} and {
			SManich
		} and {
			PTeixeira
		} and {
			MSantos
		}}
		
		
		
		
		
		
		
	
	
		,
	booktitle={{Design of Circuits and Integrated Systems Conference (DCIS98)}}
				
			,
	year={1998}
			
		
	

}

@incollection{b71,
	
	
		,
	title={{Reduction of power consumption during test application by test vector ordering}}
		,
	author={{
			PGirard
		} and {
			CLandrault
		} and {
			SPravossoudovitch
		} and {
			DSeverac
		}}
		
		
		
	
	
		,
	journal={{IEE Electronics Let-ters}}
		
			33
			21
			
			,
	year={1997}
		
	

}

@incollection{b72,
	
	
		,
	title={{Reducing power consumption during test application by test vector ordering}}
		,
	author={{
			PGirard
		} and {
			CLandrault
		} and {
			SPravossoudovitch
		} and {
			DSeverac
		}}
		
		
		
	
	
		,
	booktitle={{Proc. International Symposium on Circuits and Systems (ISCAS)}}
				International Symposium on Circuits and Systems (ISCAS)
		
			,
	year={1998}
			
		
	

}

@incollection{b73,
	
	
		,
	title={{Effective low power BIST for datapaths}}
		,
	author={{
			DGizopoulos
		} and {
			NKranitis
		} and {
			APaschalis
		} and {
			MPsarakis
		} and {
			YZorian
		}}
		
		
		
		
	
	
		,
	booktitle={{Proc. of the Design, Automation and Test in Europe Conference (DATE)}}
				of the Design, Automation and Test in Europe Conference (DATE)
		
			,
	year={2000}
			757
		
	

}

@incollection{b74,
	
	
		,
	title={{Low power/energy BIST for datapaths}}
		,
	author={{
			DGizopoulos
		} and {
			NKranitis
		} and {
			APaschalis
		} and {
			MPsarakis
		} and {
			YZorian
		}}
		
		
		
		
	
	
		,
	booktitle={{Proc. of the 18th IEEE VLSI Test Sympo-sium}}
				of the 18th IEEE VLSI Test Sympo-sium
		
			,
	year={2000}
			
		
	

}

@incollection{b75,
	
	
		,
	title={{Low power built-in self-test for datapath architectures}}
		,
	author={{
			DGizopoulos
		} and {
			MPsarakis
		} and {
			APaschalis
		} and {
			NKranitis
		} and {
			YZorian
		}}
		
		
		
		
	
	
		,
	booktitle={{Proc. of the 2nd International Work-shop on Microprocessor Test and Verification (MTV 99)}}
				of the 2nd International Work-shop on Microprocessor Test and Verification (MTV 99)
		
			,
	year={1999}
			
		
	

}

@incollection{b76,
	
	
		,
	title={{An input control technique for power reduction in scan circuits during test application}}
		,
	author={{
			CHuang
		} and {
			K.-JLee
		}}
		
	
	
		,
	booktitle={{Proc. 8th Asian Test Symposium}}
				8th Asian Test Symposium
		
			,
	year={1999}
			
		
	

}

@incollection{b77,
	
	
		,
	title={{Low-power testing for C-testable iterative logic ar-rays}}
		,
	author={{
			S.-AHwang
		} and {
			C.-WWu
		}}
		
	
	
		,
	booktitle={{Proceedings International Conference on VLSI Technology, Systems, and Applications}}
				International Conference on VLSI Technology, Systems, and Applications
		
			,
	year={1997}
			
		
	

}

@incollection{b78,
	
	
		,
	title={{An approach for multilevel logic optimization targeting low power}}
		,
	author={{
			SIman
		} and {
			MPedram
		}}
		
	
	
		,
	journal={{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}}
		
			15
			8
			
			,
	year={August 1996}
		
	

}

@incollection{b79,
	
	
		,
	title={{Estimation for maximum instantaneous current through supply lines for CMOS circuits}}
		,
	author={{
			Y.-MJiang
		} and {
			AKrstic
		} and {
			K.-TCheng
		}}
		
		
	
	
		,
	booktitle={{IEEE Transactions on Very Large Scale Integration (VLSI) Systems}}
				
			,
	year={February 2000}
			8
			
		
	

}

@incollection{b80,
	
	
		,
	title={{Tough challenges as design and test go nanometer}}
		,
	author={{
			RKapur
		} and {
			TWWilliams
		}}
		
	
	
		,
	journal={{Computer}}
		
			32
			11
			
			,
	year={November 1999}
		
	

}

@incollection{b81,
	
	
		,
	title={{High-level synthesis of low-power control-flow intensive circuits}}
		,
	author={{
			KSKhouri
		} and {
			GLakshminarayana
		} and {
			NKJha
		}}
		
		
	
	
		,
	journal={{IEEE Transactions on Computer-Aided De-sign of Integrated Circuits and Systems}}
		
			18
			
			,
	year={December. 1999}
		
	

}

@incollection{b82,
	
	
		,
	title={{Power optimisation of FPGA-based designs without rewiring}}
		,
	author={{
			BKumthekar
		} and {
			LBenini
		} and {
			EMacii
		} and {
			FSomenzi
		}}
		
		
		
	
	
		,
	journal={{IEE Proceedings -Computers and Digital Tech-niques}}
		
			147
			3
			
			,
	year={May 2000}
		
	

}

@incollection{b83,
	
	
		,
	title={{High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors}}
		,
	author={{
			GLakshminarayana
		} and {
			NKJha
		}}
		
	
	
		,
	journal={{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}}
		
			18
			3
			
			,
	year={March 1999}
		
	

}

@incollection{b84,
	
	
		,
	title={{Wavesched: A novel scheduling technique for control-flow intensive designs}}
		,
	author={{
			GLakshmi Narayana
		} and {
			KSKhouri
		} and {
			NKJha
		}}
		
		
	
	
		,
	journal={{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}}
		
			18
			5
			
			,
	year={May 1999}
		
	

}

@incollection{b85,
	
	
		,
	title={{Incorporating speculative execution into scheduling of control-flow-intensive designs}}
		,
	author={{
			GLakshminarayana
		} and {
			ARaghunathan
		} and {
			NKJha
		}}
		
		
	
	
		,
	journal={{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}}
		
			19
			3
			
			,
	year={March 2000}
		
	

}

@incollection{b86,
	
	
		,
	title={{Power management in high level synthesis}}
		,
	author={{
			GLakshminarayana
		} and {
			ARaghunathan
		} and {
			NKJha
		} and {
			SDey
		}}
		
		
		
	
	
		,
	booktitle={{IEEE Transactions on Very Large Scale Integration (VLSI) Systems}}
				
			,
	year={March 1999}
			7
			
		
	

}

@incollection{b87,
	
	
		,
	title={{An estimation-based technique for test scheduling}}
		,
	author={{
			ELarsson
		} and {
			ZPeng
		}}
		
	
	
		,
	booktitle={{Electronic Circuits and Systems Conference}}
				
			,
	year={1999}
			
		
	

}

@incollection{b88,
	
	
		,
	title={{A technique for test infrastructure design and test schedul-ing}}
		,
	author={{
			ELarsson
		} and {
			ZPeng
		}}
		
	
	
		,
	booktitle={{Design and Diagnostic of Electronic Circuits and Systems Workshop (DDECS 2000)}}
				
			,
	year={2000}
		
	

}

@incollection{b89,
	
	
		,
	title={{Test infrastructure design and test scheduling optimization}}
		,
	author={{
			ELarsson
		} and {
			ZPeng
		}}
		
	
	
		,
	booktitle={{IEEE European Test Workshop}}
				
			,
	year={2000}
		
	

}

@incollection{b90,
	
	
		,
	title={{High level power modeling, estimation, and optimization}}
		,
	author={{
			EMacii
		} and {
			MPedram
		} and {
			FSomenzi
		}}
		
		
	
	
		,
	journal={{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}}
		
			17
			11
			
			,
	year={November 1998}
		
	

}

@incollection{b91,
	
	
		,
	title={{Energy and average power con-sumption reduction in LFSR based BIST structures}}
		,
	author={{
			SManich
		} and {
			AGabarro
		} and {
			MLopez
		} and {
			JFigueras
		} and {
			PGirard
		} and {
			LGuiller
		} and {
			CLandrault
		} and {
			SPravossoudovitch
		} and {
			PTeixeira
		} and {
			MSantos
		}}
		
		
		
		
		
		
		
		
		
	
	
		,
	booktitle={{Design of Circuits and Integrated Systems Conference (DCIS99)}}
				
			,
	year={1999}
			
		
	

}

@incollection{b92,
	
	
		,
	title={{Low power BIST by filtering non-detecting vectors}}
		,
	author={{
			SManich
		} and {
			AGabarro
		} and {
			MLopez
		} and {
			JFigueras
		} and {
			PGirard
		} and {
			LGuiller
		} and {
			CLandrault
		} and {
			SPravossoudovitch
		} and {
			PTeixeira
		} and {
			MSantos
		}}
		
		
		
		
		
		
		
		
		
	
	
		,
	booktitle={{IEEE European Test Workshop (ETW99)}}
				
			,
	year={1999}
			
		
	

}

@incollection{b93,
	
	
		,
	title={{Low power BIST by filtering non-detecting vectors}}
		,
	author={{
			SManich
		} and {
			AGabarro
		} and {
			MLopez
		} and {
			JFigueras
		} and {
			PGirard
		} and {
			LGuiller
		} and {
			CLandrault
		} and {
			SPravossoudovitch
		} and {
			PTeixeira
		} and {
			MSantos
		}}
		
		
		
		
		
		
		
		
		
	
	
		,
	journal={{Journal of Electronic Testing: Theory and Applications (JETTA)}}
		
			16
			3
			
			,
	year={June 2000}
		
	

}

@incollection{b94,
	
	
		,
	title={{Theoretical bounds for switching activity analysis in finite-state machines}}
		,
	author={{
			DMarculescu
		} and {
			RMarculescu
		} and {
			MPedram
		}}
		
		
	
	
		,
	booktitle={{IEEE Transactions on Very Large Scale Integration (VLSI) Systems}}
				
			,
	year={June 2000}
			8
			
		
	

}

@incollection{b95,
	
	
		,
	title={{Probabilistic modelling of depen-decies during switching activity analysis}}
		,
	author={{
			RMarculescu
		} and {
			DMarculescu
		} and {
			MPedram
		}}
		
		
	
	
		,
	journal={{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}}
		
			17
			2
			
			,
	year={February 1998}
		
	

}

@incollection{b96,
	
	
		,
	title={{The left edge algorithm and the tree growing technique in block-test scheduling under power constraints}}
		,
	author={{
			VMuresan
		} and {
			XMuresan
		} and {
			MWang
		} and {
			Vladutiu
		}}
		
		
		
	
	
		,
	booktitle={{Proc. of the 18th IEEE VLSI Test Symposium}}
				of the 18th IEEE VLSI Test Symposium
		
			,
	year={2000}
			
		
	

}

@incollection{b97,
	
	
		,
	title={{The left edge algorithm in block-test scheduling under power constraints}}
		,
	author={{
			VMuresan
		} and {
			VMuresan
		} and {
			XWang
		} and {
			MVladutiu
		}}
		
		
		
	
	
		,
	booktitle={{Proc. Internation Symposium on Circuits and Systems (ISCAS)}}
				Internation Symposium on Circuits and Systems (ISCAS)
		
			,
	year={2000}
		
	

}

@incollection{b98,
	
	
		,
	title={{Power constrained block-test list scheduling}}
		,
	author={{
			VMuresan
		} and {
			XWang
		} and {
			VMuresan
		} and {
			MVladutiu
		}}
		
		
		
	
	
		,
	booktitle={{11th IEEE International Workshop on Rapid System Prototyping (RSP 2000)}}
				
			,
	year={2000}
			
		
	

}

@incollection{b99,
	
	
		,
	title={{Nanometer technology challenges for test and test equipment}}
		,
	author={{
			WMNeedham
		}}
	
	
		,
	journal={{Computer}}
		
			32
			11
			
			,
	year={November 1999}
		
	

}

@book{b100,
	
	
		,
	title={{Digital Integrated Circuits: A Design Perspective}}
		,
	author={{
			JMRabaey
		}}
		
			,
	year={1996}
			,
	publisher={Prentice-Hall International}
		
	

}

@incollection{b101,
	
	
		,
	title={{Simultaneous module selection and scheduling for power-constrained testing of core based systems}}
		,
	author={{
			CPRavikumar
		} and {
			GChandra
		} and {
			AVerma
		}}
		
		
	
	
		,
	booktitle={{13th Interna-tional Conference on VLSI Design}}
				
			,
	year={2000}
			
		
	

}

@incollection{b102,
	
	
		,
	title={{Evaluating BIST architectures for low power}}
		,
	author={{
			CPRavikumar
		} and {
			NSPrasad
		}}
		
	
	
		,
	booktitle={{7th Asian Test Symposium}}
				
			,
	year={1998}
			
		
	

}

@incollection{b103,
	
	
		,
	title={{A polynomial-time algorithm for power constrained testing of core based systems}}
		,
	author={{
			CPRavikumar
		} and {
			AVerma
		} and {
			GChandra
		}}
		
		
	
	
		,
	booktitle={{8th Asian Test Symposium}}
				
			,
	year={1999}
			
		
	

}

@incollection{b104,
	
	
		,
	title={{Circuit activity based CMOS logic synthesis for low power reliable operations}}
		,
	author={{
			KRoy
		} and {
			SPrasad
		}}
		
	
	
		,
	journal={{IEEE Transactions on Very Large Scale Integration (VLSI) Systems}}
		
			1
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			,
	year={December 1993}
		
	

}

@incollection{b105,
	
	
		,
	title={{Automatic test vector cultivation for sequential Bench Marking Models of Low Power VLSI Testing Strategies: Current State of the Art VLSI circuits using genetic algorithms}}
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	author={{
			DGSaab
		} and {
			YGSaab
		} and {
			JAAbrahamn
		}}
		
		
	
	
		,
	journal={{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}}
		
			15
			10
			
			,
	year={October 1996}
		
	

}

@incollection{b106,
	
	
		,
	title={{Static compaction techniques to control scan vector power dissipation}}
		,
	author={{
			RSankaralingam
		} and {
			RROruganti
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			NATouba
		}}
		
		
	
	
		,
	booktitle={{Proc. of the 18th IEEE VLSI Test Symposium}}
				of the 18th IEEE VLSI Test Symposium
		
			,
	year={2000}
			
		
	

}

@incollection{b107,
	
	
		,
	title={{The International Technology Roadmap for Semiconductors (ITRS)}}
		
	
	
		,
	booktitle={{Edition}}
				
			,
	year={1999. 1999}
		
	
	,
	note={Semiconductor Industry Association (SIA)}

}

@incollection{b108,
	
	
		,
	title={{The analysis of one-dimensional linear cellular automata and their aliasing properties}}
		,
	author={{
			MSerra
		} and {
			TSlater
		} and {
			JCMuzio
		} and {
			MMiller
		}}
		
		
		
	
	
		,
	journal={{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}}
		
			9
			7
			
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	year={July 1990}
		
	

}

@incollection{b109,
	
	
		,
	title={{Method for minimising the switching activity of two-level logic circuits}}
		,
	author={{
			GTheodoridis
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			DSoudris
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			CEGoutis
		}}
		
		
		
	
	
		,
	booktitle={{IEE Proceedings -Computers and Digital Techniques}}
				
			,
	year={September 1998}
			145
			
		
	

}

@incollection{b110,
	
	
		,
	title={{Star test: The theory and its appli-cations}}
		,
	author={{
			K.-HTsai
		} and {
			JRajski
		} and {
			MMarek-Sadowska
		}}
		
		
	
	
		,
	journal={{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}}
		
			19
			9
			
			,
	year={September 2000}
		
	

}

@incollection{b111,
	
	
		,
	title={{Two-level logic minimization for low power}}
		,
	author={{
			J.-MTseng
		} and {
			J.-YJon
		}}
		
	
	
		,
	journal={{ACM Transactions on Design Automation of Electronic Systems (TODAES)}}
		
			4
			1
			
			,
	year={January 1999}
		
	

}

@incollection{b112,
	
	
		,
	title={{Lowpower state assignment targeting two-and multilevel logic implementations}}
		,
	author={{
			C.-YTsui
		} and {
			MPedram
		} and {
			AMDespain
		}}
		
		
	
	
		,
	journal={{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}}
		
			17
			2
			
			,
	year={December 1998}
		
	

}

@incollection{b113,
	
	
		,
	title={{Maximization of power dissipation in large CMOS circuits considering spurious transitions}}
		,
	author={{
			C.-YWang
		} and {
			KRoy
		}}
		
	
	
		,
	booktitle={{IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications}}
				
			,
	year={April 2000}
			47
			
		
	

}

@book{b114,
	
	
		,
	title={{Minimizing Heat Dissipation During Test Application}}
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	author={{
			SWang
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			,
	year={May 1998}
		
	
	,
	note={PhD thesis}
	,
	note={Uni-versity of Southern California}

}

@incollection{b115,
	
	
		,
	title={{ATPG for heat dissipation minimization during scan testing}}
		,
	author={{
			SWang
		} and {
			SKGupta
		}}
		
	
	
		,
	booktitle={{Proc. 34th Design Automation Conference (DAC)}}
				34th Design Automation Conference (DAC)
		
			,
	year={1997}
			
		
	

}

@incollection{b116,
	
	
		,
	title={{DS-LFSR: A new BIST TPG for low heat dissipation}}
		,
	author={{
			SWang
		} and {
			SKGupta
		}}
		
	
	
		,
	booktitle={{Proc. IEEE International Test Conference}}
				IEEE International Test Conference
		
			,
	year={1997}
			
		
	

}

@incollection{b117,
	
	
		,
	title={{LT-RTPG: A new testper-scan BIST TPG for low heat dissipation}}
		,
	author={{
			SWang
		} and {
			SKGupta
		}}
		
	
	
		,
	booktitle={{Proc. IEEE International Test Conference}}
				IEEE International Test Conference
		
			,
	year={1999}
			
		
	

}

@incollection{b118,
	
	
		,
	title={{Powerdriven technology mapping using pattern-oriented power modelling}}
		,
	author={{
			CYeh
		} and {
			C.-CChang
		} and {
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