@incollection{, 493E40BE8031C0F50CA80EBFDD62F33A , author={{Mr. Appa RaoM.} and {Cyril Prasanna RajP.} and {JNTU College of Engineering. Ananthapur.}}, journal={{Global Journal of Researches in Engineering}}, journal={{GJRE}}2249-45960975-586110.34257/gjre, address={Cambridge, United States}, publisher={Global Journals Organisation}12111521 } @book{b0, , author={{ SHLewis } and { PRGray }} , title={{A pipelined 5}} } @incollection{b1, , title={{Msample/s 9-bit analog-todigital converter}} , journal={{IEEE J. Solid-State Circuits}} , year={Dec. 1987} , note={SC-22} } @incollection{b2, , title={{A 10 b 150 MS/s 123 mW 0.18 _m CMOS Pipelined ADC}} , author={{ S.-MYoo }} , booktitle={{IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers}} , year={Feb. 2003} } @book{b3, , author={{ TCho } and { PRGray }} , title={{A10 b}} 20 } @incollection{b4, , title={{MSample/s, 35mWpipeline A/D converter}} , journal={{IEEE J. Solid-State Circuits}} 30 , year={Mar. 1995} } @book{b5, , title={{}} , author={{ DWCline } and { PRGray }} 13 } @incollection{b6, , title={{Msamples/s pipelined analog to-digital converter in 1.2-_m CMOS}} , journal={{IEEE J. Solid-State Circuits}} 31 , year={Mar. 1996} } @incollection{b7, , title={{Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications}} , author={{ SHLewis }} , journal={{IEEE Trans.Circuits Syst. II}} 39 , year={Aug. 1992} } @incollection{b8, , title={{Systematic design for optimization of high-speed self-calibrated pipelined A/D converters}} , author={{ JGoes } and { JCVital } and { JEFranca }} , journal={{IEEE Trans.Circuits Syst. II}} 45 , year={Dec. 1998} } @incollection{b9, , title={{A 14-bit 10-MHz calibration-free CMOS pipelined A/D converter}} , author={{ LASinger } and { TLBrooks }} , booktitle={{Symp. VLSI Circuits Dig. Tech. Papers}} , year={June 1996} } @incollection{b10, , title={{A 2.5-V, 12-b, 5-Msample/s pipeline CMOS ADC}} , author={{ PCYu } and { H.-SLee }} , journal={{IEEE J. Solid-State Circuits}} 31 , year={Dec. 1996} } @incollection{b11, , title={{A 69 mW 10 b 80 MS/s pipelined CMOS ADC}} , author={{ B.-MMin } and { PKim } and { DBoisvert }} , booktitle={{IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers}} , year={Feb. 2003} } @incollection{b12, , title={{An 8 b 80 MSample/s pipelined ADC with background calibration}} , author={{ JMing } and { SHLewis }} , booktitle={{IEEE Int. Solid-State Circuits Conf. Dig.Tech. Papers}} , year={Feb. 2000} } @incollection{b13, , title={{An 8-bit 13-MSamples/s digital-backgroundcalibrated algorithmic ADC}} , author={{ EBBlecker } and { OEErdogan } and { PJHurst } and { SHLewis }} , booktitle={{Proc. Eur. Solid-State Circuits Conf}} Eur. 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II}} 46 , year={June 1999} } @incollection{b15, , title={{A 12-Bit 75-MS/s Pipelined ADC Using Open-loop Residue Amplification}} , author={{ BorisMurmann } and { BernhardEBoser }} , journal={{IEEE Journal of Solid-State Circuits}} 38 12 , year={Dec. 2003} } @incollection{b16, , title={{A 600 MS/s 5-bit pipelined analog-to-digital converter using Digital reference Calibration}} , author={{ AVarzaghani } and { CK KYang }} , journal={{IEEE Journal of Solid-State Circuits}} 41 2 , year={Feb. 2006} } @incollection{b17, , title={{Low-Power Pipeline ADC for Wireless LANs}} , author={{ JArias } and { VBoccuzzi } and { LQuintanilla } and { LEnrĂ­quez } and { DBisbal } and { MBanu } and { JBarbolla }} , journal={{IEEE Journal of Solid-State Circuits}} 39 8 , year={Aug. 2004} } @incollection{b18, , title={{An 8 b 80 MSample/s pipelined ADC with background calibration}} , author={{ JMing } and { SHLewis }} , booktitle={{IEEE Int. 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