# INTRODUCTION he FFT based OFDM uses complex exponential bases function to reduce interference hence it was replaced with wavelets to produce better performance at the cost of loss in orthogonality between the carriers [1] [2]. Mutiwavelets preserves high frequency components and also increases sensitivity better than scalar wavelets [7]. Multiwavelets show the perfect union of symmetry, orthogonally, finitely support and smoothness [8]. The design of orthogonal symmetric prefilter banks is shown with the discrete multiwavelet transform for image coding and digital communications. The new DMWT structure increases computational complexity, energy compaction ratio as well as the compression performance when applying to a VQ based image coding system[9][10]. A biorthogonal multi-wavelets filter has many characteristics, such as symmetry, compact support, orthogonality and 3-order vanishing moment [11]. The Fourier based OFDM (FFT-OFDM) use the complex exponential bases functions and it's replaced by an orthonormal wavelets in order to reduce the level of interference. It is found that OFDM based on Haarbased orthonormal wavelets (DWT-OFDM) are capable of reducing the inter symbol interference ISI and inter carrier interference ICI, which are caused by the loss in orthogonality between the carriers [1] [2]. To further improve the performance gains a new transform is implemented based on Multifilters called Multiwavelets (DMWT-OFDM). These filters shows more properties which is not achievable in other transforms (Fourier and wavelet) [3]. A most important Multiwavelets filter is the GHM filter proposed by Geronimo, Hardian, and Massopust The Multiwavelets functions coefficients are 2X2 matrices ,and they must multiply vectors instead of scalars during transformation step. Thus multifilter bank requires 2 input rows. To start the analysis algorithm and to reduce the noise effects , the preprocessing step associates given scalar input signal of length N to a sequence of length-2 vectors[4] [5]. # II. # Proposed System For Dmwt-Ofdm The block diagram of the proposed system for OFDM is depicted in figure (1). The S/P converter, the signal demapper and the insertion of training sequence are same as in DWT-OFDM. After that, a computation of IDMWT for 1-D signal is achieved by using an over-sampled scheme of preprocessing (repeated row), the IDMWT matrix is doubled in dimension compared with that of the input, which is a square matrix of NxN, where N is in power of 2. Transformation matrix dimensions is equal to input signal dimensions after preprocessing. To compute a single-level 1-D discrete multiwavelets transform, the next steps are: 1. Checking input dimensions: With input vector of length N, where N is in power of 2. 2. Constructing a transformation matrix W as in 3, using GHM low and high pass filters matrices given in 1 and 2, after substituting GHM matrix filter coefficients values, a 2NX2N transformation matrix results. 9 0 G ? ? ? ? ? ? ? ? ? ? ? ? ? ? = 0 2 10 1 0 20 1 3 G ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = 1 0 3 2 3 2 1 0 3 2 1 0 3 2 1 0 1 0 3 2 3 2 1 0 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 G G G G G G G G G G G G G G G G H H H H H H H H H H H H W ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 3. Preprocessing the input signal by repeating the input stream with the same stream multiplied by a constant ? , for GHM system functions 2 / 1 = ? . 4. Transformation of input vector which can be done by apply matrix multiplication to the 2NX2N constructed transformation matrix by the 2NX1 preprocessing input vector. # III. Software Reference Model Results In this section the simulation of the proposed DMWT-OFDM system in MATLAB version 7 are achieved. And the bit error rate (BER) performance of the OFDM system considered in different channel models, the additive white Gaussian noise (AWGN) channel, the flat fading channel, and the selective fading channel [6]. # a) Performance of dmwt-ofdm in awgn channel In this section, the result of the simulation for the proposed DMWT-OFDM system is calculated and shown in figure (3), which give the BER performance of DMWT-OFDM in AWGN channel. It is shown clearly that the DMWT-OFDM is much better than the two previous system FFT-OFDM and DWT-OFDM. This is a reflection to the fact that the orthogonal bases of the multiwavelets is much significant than the orthogonal bases used in FFT-OFDM and DWT-OFDM. # IV. Design Of Dmwt/Idmwt Architecture In this work, design and FPGA implementation of a hardware efficient DMWT architecture is carried out. The QAM modulated data which generates the I and Q channel signals are preprocessed and is modulated using IDMWT, the OFDM modulated data is transmitted through AWGN channel and is demodulated using DMWT, the base band signal is extracted using QAM demodulation. Figure 2 shows the detailed block diagram of OFDM modulation and demodulation. The input signal is considered as 1MHz signal with sampling frequency of 64Msps, the QAM modulator carrier frequency is chosen to be 64 MHz, the QAM symbols are obtained at 512Msps. The OFDM modulator has to process the modulated data at the rate of 512Msps. From the previous discussions, it is found that prior to OFDM modulation, the input samples are to be scaled and extended as 2N x 1 vector, which is the requirement for GHM based IDMWT. In order to achieve this the pre processing unit performs the scaling and extension operation, thus the incoming samples to preprocessing that are at 512Msps are preprocessed to 2N x1 with 1024 Msps. The preprocessed data is to be processed using IDMWT, this has to operate at frequency greater than 1024Msps. V. # Design Of Idmwt In this work, we select N=4, thus the QAM symbols are grouped into frames of 4 samples and is preprocessed. With N=4, the preprocessing unit extends the samples to 8 with scaling. The scaled samples are to be processed in the IDMWT with GHM wavelets of size 2N x 2N, with N=8, the GHM filter size is 8 x 8. The GHM filter for N=4 is given in equation W= ? ? ? ? ? ? ? ? ? ? ? ? 1 0 3 2 3 2 1 0 1 4 3 2 3 2 1 0 G G G G G G G G H H H H H H H H As we perform inverse IDMWT, the GHM filter coefficients are: W= ? ? ? ? ? ? ? ? ? ? ? ? 1 3 1 3 0 2 0 2 3 1 3 1 2 0 2 0 G G H H G G H H G G H H G G H H Using the above equation, the preprocessed data is modulated to generate OFDM signal. The OFDM signal using GHM filter can be mathematically represented as: [ ] [ ][ ] [ ][ ][ ] 1 2 2 2 1 2 WT NX N NX NX X Y = The above equation is implemented on FPGA. The input matrix is first stored in a memory of size Mx8, where M is an integer of size 1024. The input memory is loaded from the preprocessing unit. The controller reads the data from input memory into a intermediate memory of size 8x8, the controller also reads the corresponding GHM coefficients from memory. The input is multiplied and accumulated using dedicated multipliers on FPGA to compute the output samples. Modified DMWT architecture: In the previous section the BER performance is analyzed and now the GHM matrix coefficients were calculated and substituted in equations 1, 2and 3 the equations 4 to 11 are derived to design multiwavelets. Here it is scaled scaling factor 128. The table below shows co-efficient before and after scaling. -------------------( -------------------( -----------------( From the above equations it is found that to compute every output sample, it is required to perform minimum of 3 multiplications and 2 additions. Thus for N=4, the number of multiplications and additions are 28 multiplications and 20 additions respectively. The number of multiplications and additions are reduced by more than 50%. This reduction in multiplication and addition optimizes the design in terms of area and power requirement. It is also found that the latency of the design is 8N clock cycles, but throughput is 7N clock cycles, which is faster compared with existing design which is 8N-1. The latency and throughput can be further improved with parallel and pipelining architecture. # VII. Fpga Implementation Of Modified Dmwt/Idmwt The HDL model for the modified equations of GHM filter is developed and simulated using ModeSim. Multiple test cases are chosen to test the functionality of the modified equation and is verified against software reference model results. The functionally correct HL code is synthesized using Xilinx ISE 10.1 targetting VirtexII pro FPGA. Next section discuss the results of FPGA implementation. the design is perfectly mapped onto FPGA meeting the required design specifications. The HDL co simulation of the design is performed using simulation which is shown in Figure5 below. # HDL CO-Simulation # Conclusion In this work, we propose a modified GHM filter architecture for OFDM modulation and demodulation. Software reference model for DMWT based OFDM model is developed and simulated to find the BER performances for various SNRs. The simulation results show that the DMWT OFDM model outperforms FFT and DWT based OFDM models. The DMWT coefficients that are fractions are converted to integers and are modified to reduce the number of multiplications and additions. The reduced GHM filter coefficients are used to process the QAM modulated data, thus reducing the computation complexity and making it suitable for FPGA implementation. The modified equations are modeled using HDL and implemented on FPGA VirtexII pro. The design operates at maximum frequency of 300MHz and consumes less than 1% resources and thus is suitable for real time applications. The design can be further improved for its latency and throughput by designing a 1![Figure 1 : Block Diagram of DMWT-OFDM System](image-2.png "Figure 1 :") ![Figure 2 : DMWT-OFDM modem system](image-3.png "") 3![Figure 3 : BER performance of DMWT-OFDM in AWGN channel model.](image-4.png "FFigure 3 :") ![Figure below shows the top level block diagram of IDMWT logic for the I channel, which is similar for the Q channel. Area Optimized High Throughput IDMWT/DMWT Processor for OFDM on Virtex-5 FPGA Global Journal of Researches in Engineering Volume XII Issue vv v v IX Version I Journals Inc. (US) ear 2012 Y VI. Computation Complexity Of Idmwt As the input is of size 8 x 1 and is 8 bit per sample, every input frame is multiplied by 2N rows of GHM filter coefficients. Thus it requires 2N*2N multiplications and 2N(2N-1) additions. For of every output sample, ti requires 2N clock cycles (write data into intermediate memory) + 2N clocks for reading data from intermediate memory + 1 clock cycle for multiplication + 2N-1 clock for addition and another 2N clock cycle for write operation, thus for every output computation it requires 8N clock cycles. The latency is 8N clock cycles, throughput is 8N-1 clock cycles. In order to improve throughput and latency, it is required to modify the IDMWT architecture. In this work we propose a high speed DMWT and IDWMT architecture that is implemented on FPGA.](image-5.png "") 1![Scaled and Un scaled co-efficient y0= (54*x0+170*x1+54*x2)-](image-6.png "Table 1 :") ![4) y1= (34*x0-22*x1+53*x2+90*x3) -------------(5) y2= (38*x0+84*x1+38*x2) -](image-7.png "") ![6) y3= (53*x0-22*x1+34*x2+64*x3) -------------(7) y4= (34*x0-22*x1+53*x2-90*x3) ---------------(8) y5= (66*x0+11*x1+68*x2) -](image-8.png "") ![9) y6= (53*x0-46*x1+34*x2-64*x3) ------------(10) a) Computation complexity of reduced equation Equation above have been derived based on the modified GHM filter coefficients.](image-9.png "") 4![Figure 4 : Post Place and Route Simulation It is seen that the pre-simulation and post place and route simulation results match, thereby proving that](image-10.png "Figure 4 :") 6![Figure 6 below shows the RTL schematic of the proposed design with interconnects between the various blocks. It is a technology independent schematic.](image-11.png "Figure 6") 6![Figure 6 : RTL Schematic a) Device utilization summary](image-12.png "Figure 6 :") ![parallel and pipelined architecture for DMWT/IDMWT. XII Issue vv v v IX Version I Wei." An image coding method based on multiwavelet transform", Image and Signal Processing(CISP), 4 th International Congress on Volume: 2 ,2011 , Page(s): 607 -610. 9. Tai-Chiu Hsung,Lun, D.P.-K., Ho, K.C, "Orthogonal symmetric prefilter banks for discreate wavelet transforms"Signal Processing letters, IEEE,Vol.13, 2006.](image-13.png "") © 2012 Global Journals Inc. (US) * Research of DFT-OFDM and DWT-OFDM on Different Transmission Scenarios HZhang Proceedings of the 2 nd International Conference on Information Technology for Application (ICITA) the 2 nd International Conference on Information Technology for Application (ICITA) 2004 * Wavelet Based Multicarrier Transmission over Wireless Multipath Channels BGNegash Aug 2000 Delft University of Technology MS.c Thesis * Multiwavelet Analysis and Signal Processing MCotronei IEEE Transaction on Circuits and Systems II * The Application of Multiwavelet Filter Banks to Image Processing GStrela Strang IEEE Transaction on Image Processing 1993 * Multiwavelets: Theory and Application Strela June 1996 Ph.D Thesis, MIT * Fading Channels: Information-Theoretic and Communications Aspects EBiglieri JProakis SShamai IEEE Transactions on Information Theory 44 6 October 1998 * Investigation on mammographic image compression and analysis using multiwavelets and neural networks USRagupathy AKumar Senthil International conference (ICoBE) Page(s 2012