# Introduction

o keep pace with the Moore's law the CMOS transistors has witnessed aggressive scaling in the last decade. Due to this scaling the device sizes has become very small and many secondary effects, widely known as short channel effects (SCEs) and hot carrier effects (HCEs) plays important role in the device characteristics.

In an ever increasing need for higher current drive and better short-channel characteristics, siliconon-insulator MOS transistors are evolving from classical, planar, single-gate devices into three-dimensional devices with multiple-gates (double-, triple-or quadruple-gate devices). Multiple Gate Field Effect Transistors show great promise as an alternative to planar CMOS. They are known for their excellent immunity against SCEs due to better control of the channel by the gates. Several designs depicted in Figure 1 have been proposed including planar, vertical, fin, tri-gate and gate all around that all make use of enhanced gate control due to the action of multiple electrodes surrounding the channel [3]. Volume inversion (full inversion of the silicon film) [4] is the basic phenomenon found in thin film Multi-gate MOSFETs.

Out of these, the multi-gate transistor seems to be very promising due to its larger control on the channel as compared to the conventional MOSFETs. Recently Intel has revealed 22 nm FinFET based processor to be used in next generation highly efficient applications. However, more techniques have to be investigated for even better solution for overcoming the limitation imposed on the conventional CMOS processes. The gate all around (GAA) MOSFETs controls the channel of the transistors from all sides and hence provides better control over the channel than any other configuration. To look into various aspects of this transistor a 3D TCAD simulation has been carried out and compared for the different parameters.

II.


# Device Structure Generation

The device has been generated using the structure editor of Sentaurus TCAD of Synopsys. The channel region is lightly doped (1.0E+16/cm -3 , Boron) so that there is almost no degradation of mobility due to doping. Gate oxide chosen is silicon dioxide (SiO2) with thickness of 1 nm, to stop the gate tunneling current. The source and drain regions are heavily doped (1.0E+20/cm -3 , Arsenic) and a mid-gap metal gate (work function 4.6 eV) has been taken of varied gate height. A spacer region has been used between the source and channel region for the purpose of reducing the source/drain effect on the channel. A spacer oxide (SiO2) has been used in between gate and source/drain. The device has been simulated for its DC characteristics (threshold voltage) and analog characteristics (transconductance). A typical GAA MOSFET considered for simulation study is shown in the Figure 2. For comparison of the variation of different device parameters taken is given in Table 1.   


# Results And Discussions

These MOSFETs has been simulated for the suitability of their use at lower operating voltages. This has become important nowadays because of the quest for low power devices for longer battery life. The simulation results obtained from above devices confirms the suitability of these for low voltage applications F ig. 3 : Variation of the Vt1 for different gate lengths and different structures Figure 3 shows the variation of the Vt1 parameter extracted with inspect tool of the Sentaurus TCAD tool. Vt1 is the threshold voltage extracted at a drain current I d =0.1 µA/µm. It can be observed that the Vt1 is lower for large gate metal height and scales down with the gate length. Also Vt1 increases with the increase of the source/drain extension regions and scale downs with the gate length.

Figure 4 shows the variation of the threshold voltage (V th ) extracted by using the maximum slope intercept of the I d -V gs characteristics. It varies very similar to the V t1 but there is a sharp reduction in the threshold voltage at lower gate lengths. This is due to the reduction in charge carriers to be controlled by the gate. Due to lower threshold voltages of scaled CGAA MOSFET, it may better suit for the low voltage applications.  Figure 7 shows the variation of the output drain resistance of the CGAA MOSFET. Output drain resistance is almost same for different lengths of source/drain spacer region and scales down with the gate length. This is; however, lower for the larger gate metal height.

IV.


# CONCLUSION

The 3D simulations were carried out for varied range of gate lengths and source/drain extension regions. It has been found that the CGAA MOSFET has very good SCE immunity and is suitable to be used for low voltage low power applications. The transconductance is significantly larger and output resistance is lower at smaller gate lengths which mean it is also suitable for analog applications as well.
1![Fig. 1 : Evolution of multi-gate MOSFETs [3].](image-2.png "TFig. 1 :")
2![Fig. 2 : Structure of a cylindrical gate all around (CGAA) MOSFET used for simulations](image-3.png "Fig. 2 :")
45![Fig. 4 : Comparison of threshold voltage for different gate lengthsFigure5shows the ON state channel resistance for different gate lengths. The ON state resistance is lower for lower gate height and lower source drain extension. This is due to the increased control of the gate over the channel and reduced parasitic resistance.](image-4.png "Fig. 4 :Figure 5")

1StructureGate lengthSource/Drain extensionGate height (4.6 eV)Channel radiusSource/Drain dopingChannel dopingGate Oxide2 nm gate height16 nm 30 nm 50 nm10 nm2 nm10 nm1E+20 (Arsenic)1E+16 (Boron)1 nm (SiO 2 )10 nm gate height16 nm 30 nm 50 nm10 nm10 nm10 nm1E+20 (Arsenic)1E+16 (Boron)1 nm (SiO 2 )22 nm spacer length16 nm 30 nm 50 nm22 nm2 nm10 nm1E+20 (Arsenic)1E+16 (Boron)1 nm (SiO 2 )A TCAD Simulation Study of Cylindrical Gate All Around (CGAA) MOSFETs
			© 2012 Global Journals Inc. (US)
		
		

			

## ACKNOWLEDGEMENT

			

			

				


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