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\title{Dynamic Power Reduction in Modified Lifting Scheme Based DWT for Image Processing}
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\begin{document}

             \author[1]{Dr.  C.Chandrasekhar}

             \author[2]{Dr. S.Narayana  Reddy}

             \affil[1]{  S.V.University, Tirupathi.}

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\date{\small \em Received: 11 February 2012 Accepted: 2 March 2012 Published: 15 March 2012}

\maketitle


\begin{abstract}
        


Image compression is one of the major applications in image processing that imposes greater design challenges for VLSI design engineers in design and development of low power and high speed architectures. DWT is used in image compression for transformation of image from spatial to frequency domain. In this paper, DWT architecture based on lifting scheme is considered and dynamic power reduction is achieved with suitable modifications to the architecture and adoption of low power techniques. The interdependency of scaling and dilation coefficients is simplified to single hierarchy and thus reduces latency and increases throughput. Wallace tree multiplier and carry select adder are used in realizing 1D DWT architecture. The hierarchy in the design enables to adopt multi-stage and hierarchical clock gating technique thus reducing dynamic power. Power gating and DVFS techniques are also adopted to optimize power dissipation. The modified lifting architecture operates at a maximum frequency of 290MHz, and reduces power by more than 50%. The proposed design is implemented using 65nm TSMC low power library cells and is synthesized using Synopsys DC. The TCL scripts developed optimizes dynamic power dissipation.

\end{abstract}


\keywords{Dynamic power dissipation, DWT, Lifting Scheme, Hierarchical design, low power design ASIC implementation.}

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\let\tabcellsep& 	 	 		 
\section[{Introduction}]{Introduction}\par
WT is recommended by JPEG2000 standards as it supports features like progressive transmission, higher compression and region of interest encoding schemes. Convolution based DWT or FIR filter bank based DWT architectures occupy large area as they require more number of multipliers and adders, thus making the computations complex and time consuming. Mobile phones and other similar hand held devices that support image//video applications demand high speed and low power architectures with reduced memory size for DWT processing. There are several architectures discussed in literature to perform lifting based DWT. General approach for 2-D DWT is to apply the 1-D DWT row-wise which produces L and H subbands and then process these sub-bands columnwise to get LL, LH, HL and HH coefficients. Several architectures like direct mapped \hyperref[b1]{[2]}, folded \hyperref[b2]{[3]}, and flipping \hyperref[b3]{[4]} for single level and multi-level DWT have been proposed to implement 1-D lifting DWT . Many Author ? : HOD, Dept.of ECE SVCET, CHITTOOR, prof \& Head in Dept.of ECE, S.V.University, Tirupathi E-mail : snreddysvu@yahoo.com architectures that implement the Two-Dimensional separable Forward (2D-DWT) and Inverse DWT (2D-IDWT) in order to be applied on 2D signals have been presented in the past \hyperref[b4]{[5]}, \hyperref[b5]{[6]}, \hyperref[b6]{[7]} and \hyperref[b7]{[8]} . These architectures are consisting of filters for performing the 1D-DWT and memory units for storing the results of the transformation. Due to the fact that streaming multimedia applications -in which the DWT is presentare characterized by high throughput requirements, this imposes the need for optimizing the design of the filters in terms of speed. Moreover, portable multimedia devices require low power consumption for increasing the battery lifetime and this can be achieved by minimizing the storage size and number of memory accesses \hyperref[b8]{[9]}. Low power DWT architectures based on pipelining and parallel processing has been discussed in \hyperref[b9]{[10]} and  {\ref [11]}, in their work low power is achieved by modifying the architecture to reduce number of computations the design was implemented on FPGA. Many of the low power techniques reported in literature \hyperref[b11]{[12]}, \hyperref[b12]{[13]}, \hyperref[b13]{[14]} and \hyperref[b14]{[15]} for DWT propose modifications in the architecture level to reduce power dissipation. Power reduction can be accomplished at various levels of abstraction starting from architecture level to circuit level. Power reduction at the sub system level or at the circuit level can be accomplished when ASIC design of DWT architecture is performed. Many of the work reported in literature have restricted to FPGA implementation. In this paper, in order to demonstrate the dynamic power reduction techniques at various levels of abstraction, DWT architecture is considered as a test case for illustration. ASIC design of DWT architecture optimizing dynamic power reduction using 65nm TSMC libraries is performed.\par
Section II discusses wavelet transforms, DWT architecture and dynamic low power reduction techniques. Section III discusses proposed low power schemes for design DWT architecture sub systems. Section IV presents ASIC implementation of DWT architecture based on low power schemes. Section V discusses implementation results and performance comparison and section VI presents conclusion. 
\section[{a) DWT and Low Power Schemes}]{a) DWT and Low Power Schemes}\par
In this section, DWT architecture and low power schemes are presented. Lifting scheme based DWT architecture is considered as test case for dynamic power reduction and is briefly discussed in this section. 
\section[{i. DWT architecture}]{i. DWT architecture}\par
In wavelet analysis, signals are represented using a set of basis functions derived by shifting and scaling a single prototype function, referred to as "mother wavelet", in time \hyperref[b15]{[16]}. Wavelet transforms are closely related to tree structured digital filter banks and multiresolution analysis. A set of wavelet basis functions can be generated by translating and dilating the mother wavelet. A number of architectures have been proposed for calculation of DWT \hyperref[b1]{[2]}, \hyperref[b2]{[3]}, \hyperref[b3]{[4]}, \hyperref[b4]{[5]} and \hyperref[b5]{[6]}. The architectures are mostly folded and can be broadly classified into serial architectures (where the inputs are supplied to the filters in a serial manner) and parallel architectures (where the inputs are supplied to the filters in a parallel manner). A methodology for implementing lifting-based DWT that reduces the memory requirements and communication between the processors, when the input is broken up into blocks is presented in \hyperref[b16]{[17]}. Figure \hyperref[fig_0]{1}  [17]   The z-1 blocks are for delay, ?, ?, ?, ?, ? are the lifting coefficients and the shaded blocks are registers. 9/7 filter has been used for implementation which requires four steps for lifting and one step for scaling. The input signal xi is split into two parts even part x 2i and odd part x 2i+1 then the first step of lifting performed is given by the equations \hyperref[b16]{[17]}.\par
Then the second lifting step performed gives:\par
Then scaling is performed and the following equations are obtained:di 1 = ? (x2i + x2i+2) + x2i+1 ai 1 = ? (di 1 + di 1 -1) + x2i di 2 = ? (ai 1 + ai 1 +1) + di 1 ai 2 = ? (di 2 + di 2 -1) + ai 1 ai = ? ai 2 di = di 2 ? ?\par
The predict step helps determine the correlation between the sets of data and predicts even data samples from odd. These samples are used in the update step for updating the present phase. Some of the properties of the original input data can be maintained in the reduced set also by construction of a new operator using the update step. The lifting coefficients have constant values of -1.58613, -0.0529, 0.882911, 0.44350, -1.1496 for ?, ?, ?, ?, ? respectively. ai and di are DWT outputs after level 1 decompisition.\par
ii. Sources of power dissipation in CMOS VLSI circuits Power consumption in CMOS digital circuits is divided two major components (Static and Dynamic) as shown in Figure \hyperref[fig_3]{2 (a)}. Static power is due to leakage current and short circuit current, dynamic power is due to switching current. Power dissipation is CMOS is exponentially increased with scaling in transistor size. Figure \hyperref[fig_3]{2(b)} shows the power dissipation in CMOS with technology scaling. Dynamic power dissipation was dominating with 250nm technology, with technology scaling towards lower geometries (65nm and below), leakage power has significantly increased. However, dynamic power has also exponentially increased; this is due to the fact in increase in switching current and frequency of operation of CMOS circuits. There are various low power reduction techniques such as \hyperref[b17]{[18]}    
\section[{Global Journal of Researches in Engineering}]{Global Journal of Researches in Engineering} 
\section[{Subsystem Designs for Dwt Architecture}]{Subsystem Designs for Dwt Architecture}\par
An adder is the most commonly used arithmetic block in the Central Processing Unit (CPU) of a microprocessor, a Digital Signal Processor (DSP), and even in a variety of ASICs. In a DWT processor, adder is one of the important building blocks, required to compute the DWT coefficients of input signal. Multiplier used in a DWT processor also requires adder to add the partial products. Hence, design and analysis of adder is considered in this section. Speed and optimization of power of an adder is significant, to improve the overall performance of the system. But an adder also experiences the power-delay trade off. That is, its power dissipation increases with reduction in delay and vice versa. There are various architectures for adder design. 4-bit adders can be of different types. Some of those are Carry look Ahead Adder, Ripple Carry Adder, Carry Save Adder, Carry Select Adder. In many digital signal processing operations-such as correlations, convolutions, filtering, and frequency analysis-one needs to perform multiplication. Multiplication algorithms will be used to illustrate methods of designing different cells so that they fit into a larger structure. In order to introduce these designs, simple and serial and parallel multipliers will be introduced. High-speed parallel multipliers are becoming one of the keys in RISCs (Reduced Instruction Set Computers), DSPs (Digital Signal Processors), and graphics accelerators and so on. Parallel multipliers are used in data processor as well as in digital signal processors. There are various multiplier architectures reported in literature, Wallace tree, booths multiplier, BZ-FAD multiplier, Shift and Add multiplier and Array multiplier are most popular for DSP applications. In this work, the adders and multipliers are modeled using HDL and is synthesized using TSMC 65nm CMOS libraries using Synopsys DC. The synthesis results generate reports that provide information on area, delay and power dissipation. The results obtained are presented in table 1 and table 2 is without low power techniques. Multipliers are designed using carry save adders.  In order to reduce power dissipation of adder and multiplier, multi VDD technique is adopted. Reducing VDD supply voltage, reduce the power consumption, there will be no effect on area. From the results obtained it is found that power consumption is a quadratic function of voltage (Power= fCV DD 2 ). Decrease in supply voltage increases the overall delay (Delay = (KV DD /V DD -V t ) ? .\par
The synthesis results generate reports that provide information on area, delay and power dissipation. The results obtained are presented in table 1 and table 2 is without low power techniques. Multipliers are designed using carry save adders. Lifting equations presented in (  {\ref 1}) -(  {\ref 6}) when realized using HDL model is a sequential process, as the scaling factors and are dependent on previous samples, thus introducing latency. In order to increase throughput and latency modified equation are derived. The modified lifting equations eliminate dependency of outputs on previous samples. We have obtained the equations for a i and d i by substituting (4) in (  {\ref 3}), (  {\ref 3}) in (  {\ref 2}) and so on. The lifting coefficients were substituted and the results were scaled by multiplying with 256 to avoid decimal and to round off the values. The modified lifting scheme equations are: These equations are obtained by taking coefficients as common. The equations have initial latency, as the input samples need to be stored before DWT ai and di coefficients computations.? a i = 294* (8(6*x 2i +4*x 2i-2 +x 2i +4+x 2i+4 +x 2i-4 +4*x 2i+2\par
The design of low power architecture to reduce dynamic power dissipation is based on equations \hyperref[b6]{(7)} and \hyperref[b7]{(8)}. From the equation the following are the observations made: The proposed architecture shown in Figure \hyperref[fig_7]{4} takes two inputs and gives two outputs per cycle. Data1 and Data2 are the odd and even input samples given to hardware in single clock for 100 \% hardware utilization. This architecture is very simple design as compared to other architectures suggested in \hyperref[b19]{[20]} which have complex control path to achieve 100\% hardware utilization. The row processor and column processor shown in figure \hyperref[fig_7]{4} are realized using modified lifting scheme based equations.\par
Figure  {\ref 3} : Row processor and column processor for modified lifting DWT Based on the architecture shown in figure  {\ref 3} and equations presented in \hyperref[b6]{(7)} and (  {\ref 8}), the top level model for the architecture is shown in figure \hyperref[fig_7]{4}. A detailed data flow for the proposed architecture is presented in the The modified architecture derived consists of the following blocks: parallel input and serial output register, serial input and parallel output register, Multiplier and adders and control unit. The HDL model is developed and the design is verified for its functionality using test bench in ModelSim. The functionally correct HDL code is synthesized using Synopsys DC targeting TSMC 65 nm library and technology files. The reports obtained are complied and presented in table \hyperref[tab_4]{4}. From the results obtained and tabulated in Table \hyperref[tab_4]{4}, it is found that due to changes in architecture that reduces number of stages in DWT computation, the dynamic power dissipation is reduced be 37\%. However, the area is increased due to increase in registers and intermediate storage units, the design is synthesized to obtain minimum delay and zero slack requirement. Due to architectural changes it is demonstrated that dynamic power is reduced by 37\%. In order to further reduce power dissipation various other dynamic low power techniques are introduced for optimization. The simplest, general (or automatic) clock gating inserts a single clock gate for each register bank. Most tools permit the user "split" register banks or to prevent clock gate "sharing" across unrelated register banks. To save even more dynamic power, advanced clock gating styles such as multi-stage and hierarchical can be used, depending on design architecture and design requirements. The modified lifting DWT have common coefficients and thus need to be enabling at different instants of time and hence multi-stage clock gating technique is implemented. The 2D DWT architecture is realized using sub systems (multipliers, adders and registers), 1D DWT and finally 2D DWT, in order to reduce power dissipation hierarchical clock gating technique is adopted. Figure \hyperref[fig_5]{5} shows the multistage clock gating technique introduced into the row processor. Enable adder enables all adders together, similarly the enable reg enables all intermediate registers, thus saving power.  In order to implement power gating technique power gates and state retention register required. Power gating cells are required for turning blocks on and off. State retention registers in their turn are useful because, if the state of a shut down or "sleeping" block needs to be retained the most automated method to retain the state is the use of retention registers. These registers have a backup power supply connection that remains always on to hold the state of the register via a high voltage threshold latch built into the register. An isolation cell is required to ensure electrical and logical isolation of logic that is shut down from active logic in a design. The reason this is required is because when a block is shut down the internal signal level will transition to an unknown, floating state. Also always on cells are required between switched and steady state blocks to ensuring interoperability. Figure \hyperref[fig_11]{7} shows the power gating logic for dynamic power reduction. Multiple voltages are used to drive the cells that are active or in standby. In the hierarchical design shown in Figure \hyperref[fig_10]{6}, 1D DWT are active during computation and inactive during data storage, thus power gating techniques are inserted. The most common approach to provide state retention during power gating is to replace a standard register with a retention register. To achieve further improvements in power reduction without resorting to custom circuit techniques, Dynamic Voltage and Frequency Scaling can be used. Dynamic Voltage and Frequency Scaling is effective because of the following two facts:\par
? The amount of energy required to complete a task is proportional to the square of the supply voltage.\par
? The maximum frequency of any CMOS circuit is proportional to the supply voltage.\par
So if the supply voltage is decreased there is a square-law reduction in energy to complete a given task. However the task takes longer to complete because of the linear reduction in frequency. Therefore, the principle gain with Dynamic Voltage and Frequency Scaling is with respect to dynamic power consumption.\par
Dynamic voltage and frequency scaling adjusts performance and energy consumption levels while the logic circuit is active. It is required to reduce processor frequency and voltage to obtain quadratic energy savings. DVFS is an effective way of reducing the CPU energy consumption by providing computation power.\par
DVFS technique has been proven to be a highly effective technique for power minimization subject to a performance constraint. DVFS should consider not only the CPU power, but also the total system power dissipation. In this work, to realize 2D DWT, multiple 1D DWT architecture is realized using modified lifting scheme logic. Thus DVFS is adopted to minimize power dissipation.\par
DVFS computation for modified lifting DWT: Workload of a task, W task , is defined as the total number of clock cycles required to compute 1D DWT.  
\section[{Asic Implementation and Result Analysis}]{Asic Implementation and Result Analysis}\par
The simulation results for modified DWT are presented in this section. There are sixty four inputs, each having bit width of twenty bits. These inputs are serially sent to the DWT architecture. The DWT consists of registers, multiplexer, adder and multiplier. Whenever the inputs are sent through SIPO (serial input parallel output), the data has been divided into even data and odd data. The even data and odd data are stored in the temporary registers. When the reset is high, the temporary register value consists of zero, whenever the reset is low, the input data is split into the even data and odd data. The input data is read up to sixty four clock cycles, after that the data read according to the lifting scheme. The output data consists of low pass and high pass elements. This is the 1-D discrete wavelet    
\section[{Implementation Results and Discussion}]{Implementation Results and Discussion}\par
In this work, ASIC design flow is restricted to synthesis only for the modified lifting DWT, thus low power libraries and low power IPS from Synopsys design ware are adopted for synthesis. The synthesis constraint file is set for low power synthesis, the Synopsys DC constraints are:\par
transform. The two level discrete wavelet transform is  The constraints are set according to the command set in the file above. The low power constraints are supported only if the RTL is hierarchical and is parallel in nature. The constraints file is shown in below. The constraints for dynamic power reduction discussed earlier are set in a constraints file and are used for synthesis. The TCL scripts for DWT\textunderscore TOP\textunderscore MODULE are presented below and are used for synthesis. Figure 10 shows the synthesis netlist obtained using 65nm technology and the interconnections used in the design along with clock tree network. Figure \hyperref[fig_0]{11} shows the synthesized netlist along with clock tree network.\par
RTL model developed for the modified lifting scheme based DWT architecture is remodeled for ASIC implementation. The design is synthesized using Design Compiler and timing analysis is carried out using Prime Time. The design requires 42 input-output ports and requires 550 cells. The total combinational area is 21527.410 sq umm and non-combinational area is 10256.23 sq umm. Total dynamic power is 498.36 ?W. Due to the low power techniques adopted the dynamic power dissipation is reduced by 19\%. From the results obtained, design of architecture achieves 37\% power reduction; low power techniques presented in this section reduces power dissipation by 17\%. Thus maximum power dissipation is achieved at the architecture abstract level. Power saving achieved at various levels of hierarchy is proven in this work. Starting from architecture level to circuit level, power reduction need to be performed and is illustrated in this work.\par
V. 
\section[{Conclusion}]{Conclusion}\par
In this work, a modified lifting based DWT is proposed, designed and implemented using 64nm TSMC low power design library. Lifting based DWT is considered to illustrate the techniques that can be adopted to reduce dynamic power. Modification in the architecture level as well as at different abstraction levels are considered for power reduction. Low power library cells from Synopsys design ware are considered for synthesis. TCL scripts for constraining the design for various dynamic power dissipation are developed. The RTL model developed is synthesized and performances are estimated. From the results obtained it is found that there is a total of 50\% power reduction as compared with direct implementation. The developed low power techniques can be adopted to other complex designs. Further power dissipation can be reduced at the physical design stage.   
\section[{VI.}]{VI.} 
\section[{Parameters}]{Parameters}\begin{figure}[htbp]
\noindent\textbf{1}\includegraphics[]{image-2.png}
\caption{\label{fig_0}Figure 1 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-3.png}
\caption{\label{fig_1}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-4.png}
\caption{\label{fig_2}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{2}\includegraphics[]{image-5.png}
\caption{\label{fig_3}Figure 2 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-6.png}
\caption{\label{fig_4}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{5}\includegraphics[]{image-7.png}
\caption{\label{fig_5}) - 5 *}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-8.png}
\caption{\label{fig_6}?}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{4}\includegraphics[]{image-9.png}
\caption{\label{fig_7}Figure 4 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-10.png}
\caption{\label{fig_8}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{5}\includegraphics[]{image-11.png}
\caption{\label{fig_9}Figure 5 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{6}\includegraphics[]{image-12.png}
\caption{\label{fig_10}Figure 6 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{7}\includegraphics[]{image-13.png}
\caption{\label{fig_11}Figure 7 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-14.png}
\caption{\label{fig_12}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-15.png}
\caption{\label{fig_13}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{8}\includegraphics[]{image-16.png}
\caption{\label{fig_14}Figure 8 :}\end{figure}
     \begin{figure}[htbp]
\noindent\textbf{1} \par 
\begin{longtable}{}
\end{longtable} \par
 
\caption{\label{tab_1}Table 1 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{2} \par 
\begin{longtable}{}
\end{longtable} \par
 
\caption{\label{tab_2}Table 2 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{3} \par 
\begin{longtable}{P{0.4322857142857143\textwidth}P{0.019428571428571427\textwidth}P{0.15057142857142855\textwidth}P{0.18942857142857142\textwidth}P{0.05828571428571429\textwidth}}
Type of\tabcellsep \tabcellsep No. of\tabcellsep \multicolumn{2}{l}{Power -Delay}\\
adder (16 -\tabcellsep bit)\tabcellsep \multicolumn{2}{l}{transistors ?W}\tabcellsep -ps\\
Ripple carry\tabcellsep \tabcellsep 286\tabcellsep 40.5505\tabcellsep 600\\
adders\tabcellsep \tabcellsep \tabcellsep \\
Carry save\tabcellsep \tabcellsep 92\tabcellsep 18.9241\tabcellsep 74\\
adder\tabcellsep \tabcellsep \tabcellsep \\
Carry select\tabcellsep \tabcellsep 102\tabcellsep 16.897\tabcellsep 65\\
adder\tabcellsep \tabcellsep \tabcellsep \\
Carry look\tabcellsep \tabcellsep 621\tabcellsep 55.1482\tabcellsep 62\\
\multicolumn{2}{l}{ahead adder}\tabcellsep \tabcellsep \end{longtable} \par
 
\caption{\label{tab_3}Table 3 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{4} \par 
\begin{longtable}{P{0.85\textwidth}}
DWT\end{longtable} \par
 
\caption{\label{tab_4}Table 4 :}\end{figure}
 			\footnote{© 2012 Global Journals Inc. (US) Dynamic Power Reduction in Modified Lifting Scheme Based DWT for Image Processing} 			\footnote{© 2012 Global Journals Inc. (US)} 		 		\backmatter   			 
\subsection[{Acknowledgement}]{Acknowledgement}\par
The authors would like to acknowledge Dr. Cyril Prasanna Raj P, for his valuable support and guidance extended in completion of this work. 			  			  				\begin{bibitemlist}{1}
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