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\title{Gate Level Design of a Digital Clock with Asynchronous-Synchronous Logic}
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             \author[1]{Dr. Sheikh Md. Rabiul  Islam}

             \author[2]{Md. Jobayer  Hossain}

             \affil[1]{  }

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\date{\small \em Received: 4 February 2012 Accepted: 5 March 2012 Published: 15 March 2012}

\maketitle


\begin{abstract}
        


A digital clock has been designed at gate level and is being presented in this paper. The clock architecture consists of three major blocks SECOND,MINUTE and HOUR. The architecture is the amalgam both of synchronous and asynchronous logic. All the flip-flops at each block run synchronously. The triggering operation of a block is asynchronous in nature. It serves the design requiring lower power consumption, provides lesser noise and electromagnetic interference, lower delay and greater throughput. The clock is designed at Xilinx System Generator, synthesized with Xilinx Synthesis Tool (XST) and Simulated by Vegilogger Pro 6.5.

\end{abstract}


\keywords{Counter, asynchronous counter, synchronous counter, system level design, gate level design, GALS.}

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\let\tabcellsep& 	 	 		 
\section[{INTRODUCTION}]{INTRODUCTION}\par
digital clock is a type of clock that displays the time digitally. Instead of the rotary mechanism of electromechanical clock, it uses digital counters that count second, minute and hours. Each sixty seconds make a minute and each sixty minutes an hour. After twenty four hours the clock resets and starts from initial condition. The functional unit of a digital clock is a counter that represents a second, minute or hour block.\par
A counter \hyperref[b2]{[7]} may be defined as a register i.e. a group of flip-flops that goes through a predetermined sequence of states upon the application of input pulses. The logic gates in a counter are connected in such a way as to produce a prescribed sequence of binary states in the register.\par
There are two types of input/output (I/O) synchronization technique to design a counter [10]: synchronous and asynchronous technique. In an asynchronous counter, the flip-flop output transition serves as a source for triggering other flip-flops. In otherwords, the CP inputs of all flip-flops (except the first) are triggered not only by the incoming pulses but rather by the transitions that occur in other flip-flops. The asynchronous counter is also referred to as overlapped counter. A problem \hyperref[b2]{[7]} in designing an asynchronous logic is that it cannot be described by Boolean equations developed for describing clocked sequential circuits. Again as output of one flip-flop acts as the input of another one, the system designed at asynchronous logic faces considerable delay. On the other hand, a synchronous circuit [13] is a digital circuit in which the parts are synchronized by a single clock signal. In an ideal synchronous circuit, every change in the logical levels of its storage components is simultaneous. These transitions follow the level change of a special clock signal. Ideally, the input to each storage element has reached its final value before the next clock occurs, so the behavior of the whole circuit can be predicted exactly. Practically, some delay is required for each logical operation, resulting in a maximum speed at which each synchronous system can run  {\ref [13]}. Thus in a synchronous counter \hyperref[b2]{[7]} all the flip-flops are clocked simultaneously. The decision whether a flip-flop is to be complemented or not is determined from the values of the T inputs at the time of pulse. If T=0, the flip-flop remains unchanged. If T=1, the flip flop complements. Thus the states of the counters get changed. Synchronous logic suffers from some disadvantages: As the clock is usually a high-frequency signal, this distribution consumes a relatively large amount of power and dissipates much heat. Even the flip-flops that are doing nothing consume a small amount of power, thereby generating waste heat in the chip  {\ref [12]}. Again the maximum possible clock rate is determined by the slowest logic path in the circuit, otherwise known as the critical path. This means that every logical calculation, from the simplest to the most complex, must complete in one clock cycle. In spite of these drawbacks synchronous counters are more suited for some reasons.\par
At an asynchronous counter [11], [14] the output of any flip-flop (except the first) depends solely upon the output of the previous T flip-flop. Due to the RC time delay at each transistor there occurs a large aggregation of delay time after several flip-flops \hyperref[b3]{[8]}. So to design asynchronous counter is impractical. For this reason synchronous logic has been adopted to construct counter blocks. In addition to this the synchronous technique serves greater throughput and much lower overhead for its design simplicity \hyperref[b4]{[9]}.\par
In the way to integrated circuit implementation process way can notice two major steps \hyperref[b6]{[3]}: Design stage and fabrication stage. Design stage includes system design, logic design and mask layout preparation. At the system level design \hyperref[b8]{[4]} theA Global Journal of Researches in Engineering Volume XII Issue v v v v IV Version I 17 ( D D D D )\par
into aggregation of registers \hyperref[b4]{[9]}. Here each item represents a particular logic function. If that particular logic functions are represented by logic gates such as AND, OR or XOR, then it is called Gate level design \hyperref[b10]{[6]}. Gate level design realizes intensive aggregation of elements at much lower area. To solve the problems associated both with synchronous and asynchronous logic the author adopted a recently emerged logic structure GALS \hyperref[b0]{[1]}, \hyperref[b1]{[2]}. Globally Asynchronous Locally Synchronous logic is the amalgam of the two logics. It not only removes the drawbacks but also provides more advantages  {\ref [16]}. The advantages include lower power consumption and electromagnetic interferences.  Therefore, the flip-flop in the lowest order position is complemented with every pulse. This means that its T input must be maintained at logic 1. A flip flop in any other position is complemented with a pulse provided all the bits in the lower order positions are equal to 1. As the input functions T's of the flip flops are configured, after the desired sequence (111011 for second and minute block) comes, all the outputs of the flip flops will be 0.\par
When the second block reaches to 59 (111011 in binary), all the flip flops of this second block resets.   V. 
\section[{SYNTHESIS}]{SYNTHESIS}\par
The model is designed at Xilinx System Generator. Then it is synthesized with Xilinx Synthesis Tool (XST) as shown in Fig.  {\ref 4\&5}.\par
The outcomes include a IC package with two input ports: : RESET and CLOCK PULSE and seventeen output ports. The RTL(Register Transfer Level) schematic of the design is provided as in Fig. \hyperref[fig_5]{6(a),(b),(c)\&(d}).It assembles logic gates which meet the systems requirements \hyperref[b10]{[6]}. The details description of Pin numbers for the design of clock is given in Table \hyperref[tab_1]{.}1. Fig.  {\ref 4} : RTL schematic diagrams found from XST (system level).    
\section[{SIMULATION}]{SIMULATION}\par
The simulation of the design was run at verilolgger pro 6.5. The result was the exact replica of our expectation. From the timing diagram at Fig. \hyperref[fig_7]{7} we can notice that initially all the flip-flops are at initial state (zero state) when RESET is at state 0. The rest part of the circuitry remains inactive until RESET is at state 1. When RESET is at state 1 the flip-flops are allowed to follow counting. The state of SECOND block changes as 000000, 000001, 000010, 000011 and so on. When it reaches state 111011 (i.e. 59 in decimal), a clock pulse goes to MINUTE block and its state changes from 000000 to 000001 and the SECOND block starts counting again from 000000 state. Thus after 60 minutes when state 111011 appears at MINUTE block it resets and the state of HOUR block changes from 00000 to 00001. After counting 23 hour 59 minutes and 59 seconds, all the flip flops of the system get reseted (i.e. zero state) when the next clock pulse appears at the SECOND block. 
\section[{VII.}]{VII.} 
\section[{LIMITATIONS}]{LIMITATIONS}\par
The digital clock that is designed can count seconds, minutes and hours only. But at the real world people are not satisfied at this. They are interested in having notified other information such as date, month, year etc. It is also expected that the clock will serve some other facilities such as alarm, reminder etc. These features can be added just extending the design a little bit further. Again the design includes lesser number of gates. So it will be cost-inefficient to design on an entire chip. The author wishes to design a complete package of digital clock at the near future that will overcome the remaining drawbacks. Logic gate level design of a digital clock has been presented. The design comprises the amalgam of synchronous and asynchronous techniques to attain its purpose. The Gate level design realizes intensive aggregation of components at smaller size of the chip. Again the combinational structure assumes lower power requirement, electromagnetic interference and greater throughput. The designed structure was synthesized using XST and simulated at verilogger pro 6.5. The design was successfully loaded at Xilinx FPGA device, MDA-ASIC2 (XC25150). In spite of having some limitations the design has been found to be useful enough.  
\section[{Global Journal of Researches in Engineering}]{Global Journal of Researches in Engineering}\begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-2.png}
\caption{\label{fig_0}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{12}\includegraphics[]{image-3.png}
\caption{\label{fig_1}Fig. 1 :Fig. 2 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-4.png}
\caption{\label{fig_2}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{3}\includegraphics[]{image-5.png}
\caption{\label{fig_3}Fig. 3 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{6}\includegraphics[]{image-6.png}
\caption{\label{fig_4}Fig. 6 (}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{6}\includegraphics[]{image-7.png}
\caption{\label{fig_5}Fig. 6 (}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-8.png}
\caption{\label{fig_6}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{7}\includegraphics[]{image-9.png}
\caption{\label{fig_7}VolumeFig. 7 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-10.png}
\caption{\label{figure10}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{} \par 
\begin{longtable}{}
\end{longtable} \par
 
\caption{\label{tab_0}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{.} \par 
\begin{longtable}{P{0.13019693654266956\textwidth}P{0.11903719912472648\textwidth}P{0.0948577680525164\textwidth}P{0.13949671772428884\textwidth}P{0.36641137855579864\textwidth}}
Pin type\tabcellsep Pin\tabcellsep Pin\tabcellsep Description\tabcellsep Function\\
\tabcellsep name\tabcellsep no.\tabcellsep \tabcellsep \\
Input\tabcellsep clk,\tabcellsep 1,2\tabcellsep Single bit\tabcellsep clk is the line with input\\
\tabcellsep reset\tabcellsep \tabcellsep binary\tabcellsep signal period=1second\\
\tabcellsep \tabcellsep \tabcellsep \tabcellsep resets resets the clock to\\
\tabcellsep \tabcellsep \tabcellsep \tabcellsep zero state\\
Output\tabcellsep ah,bh,ch,\tabcellsep 3,6,9,12,\tabcellsep Single bit\tabcellsep Pins that jointly show time in\\
(Hour block)\tabcellsep dh,eh\tabcellsep 15,\tabcellsep binary\tabcellsep hour\\
Output\tabcellsep am,bm,c\tabcellsep 4,7,10,13,\tabcellsep Single bit\tabcellsep Pins that jointly show time in\\
(Minute block)\tabcellsep m,dm,\tabcellsep 16,18\tabcellsep binary\tabcellsep minute\\
\tabcellsep em,fm\tabcellsep \tabcellsep \tabcellsep \\
Output\tabcellsep as,bs,cs,d\tabcellsep 5,8,11,14,\tabcellsep Single bit\tabcellsep Pins that jointly show time in\\
(Second block\tabcellsep s,es,fs\tabcellsep 17,19\tabcellsep binary\tabcellsep second\end{longtable} \par
 
\caption{\label{tab_1}Table . 1}\end{figure}
 			\footnote{© 2012 Global Journals Inc. (US)} 			\footnote{© 2012 Global Journals Inc. (US) Fig.6(c) : Gate level representation of block FDRE.} 		 		\backmatter  			  				\begin{bibitemlist}{1}
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\end{document}
