@incollection{,
	
					
					
					CB6B30F0AFB936387C2820DBE651EBA2
				,
	author={{Dr. Sheikh Md. RabiulIslam} and {Md. JobayerHossain} and {}},
	journal={{Global Journal of Researches in Engineering}},
	journal={{GJRE}}2249-45960975-586110.34257/gjre,
	address={Cambridge, United States},
	publisher={Global Journals Organisation}1241722
}

@book{b0,
	
	
		,
	title={{Lowering Power Consumpsion in Clock by using Globally Asynchronous Locally Synchronous Design Style}}
		,
	author={{
			AHemaini
		} and {
			TMeincke
		} and {
			SKumar
		} and {
			APostula
		} and {
			TOlsson
		} and {
			PNilson
		} and {
			JOberrg
		} and {
			PEllervee
		}}
		
		
		
		
		
		
		
		1999 ACM 1- 58113-109-7/99/06
		
			99
			,
	address={New Orleans, Louisiana}
		
	

}

@book{b1,
	
	
		,
	title={{Synchronous Design Flow for Globally Asynchronous Locally Synchronous Systems}}
		,
	author={{
			JonasCarlson
		} and {
			KentPalmnvist
		} and {
			LarsWanhammar
		}}
		
		
		
	

}

@book{b2,
	
	
		,
	author={{
			MMorisMano
		}}
		,
	title={{Digital Logic and Computer design. ©1979 by}}
				
			,
	publisher={Prentice Hall}
		
	

}

@book{b3,
	
	
		,
	title={{Design of VLSI Systems-A Practical Introduction}}
		,
	author={{
			EMLinda
		} and {
			Brackenbury
		}}
		
		
	

}

@book{b4,
	
	
		,
	title={{CMOS VLSI design}}
		,
	author={{
			HENeil
		} and {
			DavidWeste
		} and {
			AyanHarris
		} and {
			Banerjee
		}}
		
		
		
		
	
	,
	note={third edition}

}

@book{b5,
	
	
		,
	title={{Gate Level Design of a Digital Clock with Asynchronous-Synchronous Logic Fig.5 : RTL schematic diagrams found from XST}}
		
	
	,
	note={showing block level}

}

@book{b6,
	
	
		,
	title={{An Overview of the Silicon Very-Large-Scale-Integration Implementation}}
		,
	author={{
			FEBarber
		} and {
			TJBartoli
		} and {
			RLFreyman
		} and {
			JAGrand
		} and {
			JKane
		} and {
			Kershaw
		}}
		
		
		
		
		
		
	

}

@incollection{b7,
	
	
	
	
		,
	booktitle={{©1981 American Telephone and Telegraph Company}}
				
			,
	year={September 1981}
			60
		
	
	,
	note={printed in USA}

}

@book{b8,
	
	
		,
	title={{A fully Asynchronous Digital Signal Processor using Selftimed Circuit" Solid-State ircuits Conference}}
		,
	author={{
			GordonMJacobs
		} and {
			RobertWBrodersen
		}}
		
		
			,
	year={1990. 1990. Feb. 1990. August 2002}
			
		
	
	,
	note={IEEE International I Issue Date}

}

@incollection{b9,
	
	
		,
	title={{Self Timed Logic using Current-Sensing Completion Detection CSCD)}}
		,
	author={{
			MarkEDean
		} and {
			DavidLDill
		} and {
			MarkHorowitz
		}}
		
		
	
	
		,
	journal={{Journal of VLSI Signal Processing}}
		
			7
			
			,
	year={1994. 1994Kluwer}
			,
	publisher={Academic Publisher}
		
	
	,
	note={Manufactured in Netherland}

}

@book{b10,
	
	
		,
	title={{Basic Logic Design with Verilog HDL: Gate Level Design on Combinational Circuits}}
		,
	editor={Chen-han Tsai, Chih-hao-Chao, Xin_Yu Shi, Bo-Yuan Peng and Bo-Yuan Peng}
		
	

}