# INTRODUCTION

rigate is a new technology which controls gate current using three wing around silicon dioxide of MOSFET. This device is called nanowire when its gate length is less than 100nm. Wave function penetration becomes vital role when cross section area of silicon of MOSFET becomes less than 10x10nm. We will consider 7x7 nm cross section area of silicon and channel length will be 20nm. Which is shown in figure (1). We also consider ?????? 2 as insulator and Aluminum as electrode in our experiment. It is necessary to know the capacitance-voltage characteristics of trigate MOSFET whenever we implement this type of MOSFET. As transistor per chip is reducing day by day so we have to consider quantum mechanics not classical mechanics because quantum mechanics give actual probability of C-V characteristics than classical mechanics. To get actual result from quantum mechanics we used here self -consistent of Schrödinger-Poisson's solver. Capacitance has mainly three region 1) accumulation region 2) depletion region and 3) inversion region. Actually inversion layer becomes volume inversion in our selected area this is cause of quantum effect.


# II.


# THEORY

Figure1 : Cross section area of trigate MOSFET. Where Qg = the charge on the electrically interconnected gate.

?s(y)=surface potential as a function of the position y along the length of the transistor.

The inversion charge in the body is divided between the source and drain terminals using the Ward-Dutton charge partition approach [1].

The charge on source terminal (Qs) is: Vfb= the flat band voltage.

Using charge conservation, the charge on drain terminal (Qd) can be expressed as:

(3)

The surface potential as a function of the position y along the length of the transistor (?s(y)) is obtained using current continuity. Current continuity states that the current is conserved all along the length of the transistor. It is well known that direct tunneling currents become significant in this regime and that the penetration of the wave function cannot be neglected [2]- [3], the capacitance of NMOS capacitors in the inversion region accounting for wave function penetration into the gate dielectric. The physical basis has been presented in [4] and [5].

In this work, the Schrodinger and Poisson equations are solved self consistently assuming that the wave function penetrates the gate dielectric. The wave function is assumed to go to zero at some point deep inside the substrate, while a traveling wave boundary condition is imposed at the gate dielectric-gate electrode interface. The wave function inside the gate dielectric is connected to the asymptotic wave function in the gate electrode using the quantum transmitting boundary method [6].

The gate capacitance under strong-inversion conditions can be described by the equivalent circuit shown in Figure 3 consisting of the oxide capacitance Cox and the inversion-layer capacitance Cinv [7], [8]. The latter includes the contributions of both the electrostatic capacitance Ces,Si and the quantum capacitance Cq [9] of the layer. While Ces,Si is related to the average distance of the channel electrons from the Si/SiO2 interface, Cq is related to the density of states (DOS) in the inversion layer. 


# RESULT AND DISCUSSION

In the text [2], Schrodinger's equation has been solved by forcing the wave function to zero at the dielectric-gate electrode boundary.

The C-V characteristics have come by solving Schrodinger-Poisson equation. These figure indicate that how wave function penetration play vital role in the case of small thickness of oxide. In our simulation we present wave function penetration in the gate electrode rather than classical mechanics.

The C-V calculated assuming such a border condition differs by an immaterial quantity from the C-V calculated by letting the wave function penetrate into the gate electrode. The classical and quantum-mechanical C-V individuality with and without wave function penetration for a metal-Si?? 2 -Si system of gate oxide thicknesses 0.5 nm and 3.0 nm are exposed in Figs. 4 and 5 correspondingly. The capacitances are normalized to the strong inversion.

Classical capacitance values to help comprehend the impact of accounting for wave function penetration. It can be undoubtedly seen that the impact is larger for the 0.5 nm gate oxide case. There are two effects that contribute to the considerably superior impact for the 0.5 nm case. They are 1) the field across the 3 nm gate oxide device is weaker than the field across the 0.5 nm device and 2) the percentage contribution of the shift of the wave function closer to the interface is larger for the 0.5 nm gate oxide device the impact of this shift would be larger for the thinner oxide case. The C-V simulations discussed thus far were performed on devices with a metal gate. However, despite detrimental effects, poly silicon is still being used as the gate electrode. Hence, simulations were also performed with poly silicon replacing the metal as the gate electrode. The simulation results (Figure 6) show that the wave function shift in the wave function influences the C-V significantly only for poly doping of greater than cm. This seems to indicate that the poly-depletion effect dominates over the shift effect due to wave function penetration and the models developed so far seem sufficient. It must, however, be pointed out that as the devices are scaled down to sub-20 nm gate lengths, metal gate electrodes will have to be used to obtain lower effective oxide thicknesses and higher capacitance values. Thus when metal gate electrodes are used the effect of wave function penetration will have to be considered.

Accounting for wave function penetration into the gate electrode causes a shift in the wave function closer to the interface, the more so the greater the voltage. This bias dependent shift results in a lower electrical oxide thickness and hence higher gate capacitance. The poly depletion effect is dominant over the wave function penetration effect. However, this effect is significant when highly doped poly silicon gates are used and will become significant when metal gate electrodes are used and the oxide thickness is reduced.   7 a continuous increase in the C G / C ox ratio can be observed as the channel cross section is scaled below 7 nm x 7 nm. We have actually observed an increase in the C G / C ox ratio when the channel cross section is scaled below 7 nm x 7 nm. We have related this to quantum effects since no increase in C G / C ox has been observed from classical calculations. The gate capacitance of trigate MOS structures is affected by quantum effects mainly via the spatial electron distribution. The quantum effects on C q have been found to be less important for the gate capacitance except for very small cross sections in the order of 2 nm x 2 nm.

IV.


# CONCLUSION

A comprehensive analysis of the effects of wave function penetration on the capacitance of NMOS capacitors has been performed. The study reveals that accounting for wave function penetration into the gate dielectric causes carrier profile to be shifted closer to the gate dielectric reducing the electrical oxide thickness. This shift increases with increasing gate voltage. In our work we present Capacitance-Voltage characteristics of Trigate MOSFET considering wave function penetration which is necessary for implementing Integrated Circuit in real life. We hope it will be helpful instrument for working in practical life.
2![Figure 2 : Schematic of the symmetric common-gate DG-FET under study. The I-V model is adequate only for describing the DC behavior but for transient description the capacitances are absolutely essential. The intrinsic capacitances of the transistor are derived from the terminal charges. The charge on the top and bottom gate electrodes is equal to total charge in the body. The](image-2.png "Figure 2 :F")
![gate voltage. Qbulk =bulk charge= ?pert =perturbation potential.](image-3.png "")
![?s(y) can be related to ?S and ?D by ?D= the surface potential at the drained . ?S = Surface potential at source terminal. Where Where Vch(y)=the channel potential. ?0(y) = the potential at the center of the body. The terminal charges are obtained by substituting ?s(y) in Eqs. (1-3) and evaluating the integrals Global Journal of Researches in Engineering Volume The expressions for terminal charges are continuous and are valid over sub-threshold, linear and saturation regimes of operation. The terminal charges are used as state variables in the circuit simulation. All the capacitances are derived from the terminal charges to ensure charge conservation. The capacitances are defined as: (5) Where, i and j denote the multi-gate FET terminals. Note that Cij satisfies (6) Effect of Quantum mechanics on capacitances Using a self-consistent Schrodinger-Poisson solver, we can analyze the effect of wave function penetration on the capacitance. The study reveals that accounting for wave function penetration into the gate dielectric causes carrier profile to be shifted closer to the gate dielectric reducing the electrical oxide thickness. This shift increases with increasing gate voltage. This shifting results in an increased capacitance.](image-4.png "F")
3![Figure 3 : Equivalent circuit for the gate capacitance in silicon MOS structures Where Cq=quantum capacitance. Ces,si= electrostatic capacitance. Cox= oxide capacitance . Cinv= inversion-layer capacitance. III.](image-5.png "Figure 3 :")
45![Figure 4 : Normalized classical and quantum mechanical capacitance obtained with and without wave function penetration for 0.5 nm oxide capacitor.](image-6.png "Figure 4 :FFigure 5 :")
6![Figure 6 : Capacitance values for a 1.0 nm gate oxide capacitor with different doping with and without wave function penetration.](image-7.png "Figure 6 :")
7![Figure 7 : C ox in series and C q and gate capacitance normalized to the C ox of trigate MOS structures as a function of the silicon cross section. (Full symbols) Quantum-mechanical and (open symbols) classical results are compared.](image-8.png "Figure 7 :")
Capacitance-Voltage characteristics of nanowire trigate MOSFET considering wave functionpenetration0.90.85Si TG t ox =1nmV Gate -V th =0.5VCL,C Gate QM,C Gate0.80.75C/C ox0.70.650.60.550.51234567891011t s i =w s i (nm)19Volume XII Issue v v v v II Version ID D D D )(Global Journal of Researches in Engineering© 2012 Global Journals Inc. (US) 2012 ebruary F
			© 2012 Global Journals Inc. (US)
		
		
			

				


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