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\title{VHDL Design of FPGA Arithmetic Processor}
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             \author[1]{  Ms.U.Sowmmiya}

             \affil[1]{  Anna University,Chennai}

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\date{\small \em Received: 9 September 2011 Accepted: 4 October 2011 Published: 19 October 2011}

\maketitle


\begin{abstract}
        


This paper involves the design and development of   a single chip VHDL FPGA  processor which performs all   arithmetic and logical functions and the output is   displayed by   means of LCD interface. This processor can perform 2n   number of operations, where n is the  number of control bits. In   this design, a 5 bit control input is used so that the processor   is  capable of performing up to 32 operations. The chip is   designed to execute 21 operations for  different specified   functions and 11 more operations can be worked on for   improvements and  future works. Two data with a size of 8 to   16 bits can be applied as input and the results are  obtained on   4 to 8 hexadecimal digits carrying 32 bits in all. A status flag is   also designed with  the features such as indication of overflow,   carry, borrow and zero value. To implement the  above design,   Very High Speed Description Language simulation is required   which can be  performed using Altera or Xilinx softwares. Once   the program has been developed, the authors  demonstrate   the feasibility of the proposed design by incorporating it into a   FPGA chip and the  required hardware can be brought into   effect. The state of each output bit is shown by using  Light   Emitting Diodes. Based on users needs, more features can be   added to the designed  hardware without hindering the   implemented one.  

\end{abstract}


\keywords{VHDL, FPGA, Processor, Chip, Arithmetic, LCD, Light Emitting Diodes, overflow, carry, borrow.}

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\let\tabcellsep& 	 	 		 
\section[{INTRODUCTION}]{INTRODUCTION}\par
Author : Professor, Department of Electronics and Communication Engineering, Apollo Engineering College, Anna University, Chennai, India.Mobile: 91-95975-32611.E-mail : klymurthy@yahoo.com Author : Lecturer, Department of Electrical and Electronics Engineering, Apollo Engineering College, Anna University, Chennai, India.Mobile: 91-98403-86834 . E-mail : sowmmeee@gmail.com II. 
\section[{RATIONALE}]{RATIONALE}\par
An early design involved in the computations of arithmetic and logical operations were complex and found to be time consuming. The circuitry needed to develop such an ALU of required specifications by conventional approach will lead to thousands of gates, transistors, resistors, capacitors, inductors and other digital components. The implementation of such a system raises major questions in the shape of its integration and optimization. These problems have been eliminated in this project by the use of Field Programmable Gate Array (FPGA) technology and by Hardware Descriptive Language (HDL). Since the feeding units are of binary nature and output of Hexadecimal, the complex and time consuming computations in the earlier methods are eliminated. The software interface along with the advanced options like graphical blocks, chip design and planner reduces the complexity and increases the ease of computations. 
\section[{III.}]{III.} 
\section[{TECHNICAL WORK PREPARATION}]{TECHNICAL WORK PREPARATION}\par
The organization and designing of this process is put forth by various tools. These tools and methods are significant in differentiating a successful one with the one carrying loop holes and discrepancies. In the present case, ALU is bricked up using synthesized operations in the form of objectives and broader aspects. The organization chart for the paper design that is needed to implement is shown in Fig. \hyperref[fig_0]{1}.  his paper deals with the design methodology of a FPGA Arithmetic Processor using VHDL to enhance the description, simulation and hardware realization. The design and implementation of FPGA based Arithmetic Logic Unit is of core significance in digital technologies as it is being an integral part of all microprocessors. As the name suggests, this is a system which is capable of performing not only arithmetic operations but also computes logic functions and provides the output through gating circuitry. All the modules described in the design are coded using VHDL which is a very useful tool with its degree of concurrency to cope with the parallelism of digital hardware. The toplevel module connects all the stages into a higher level. Once identifying the individual approaches for input, output and other modules, the VHDL descriptions are run through a VHDL simulator, followed by the timing diagrams for the verification, working and performance of the above design along with the hardware implementation that shows the appropriateness of the design. The operational overview deals with two kinds of operations which an ALU can perform. First part deals with arithmetic computations and is referred to as Arithmetic Unit. It is capable of addition, subtraction, multiplication, division, increment and decrement. The second part deals with the Gated results in the shape of AND, OR, XOR, inverter, rotate, left shift and right shift, which is referred to as Logic Unit. The functions are controlled and executed by selecting operation or control bits. A select input of 5 bit size that will accommodate up to 32 operations is sufficient to achieve the objectives. The operations selected by the Control Unit are shown in the Fig.  {\ref 2}. Arithmetic part is quite complex as compared to logic unit and involves an additional carry input. Multiplication and Division also increases the complexity of ALU. In the Logic Block, gates such as AND, OR, XOR and NOT operations are shown. Logic Block of ALU does not need as many gates as required in Arithmetic Unit and if done separately, the LOGIC unit can be implemented using Complex Programmable Logic Devices (CPLD) or other Programmable Logic Device (PLD) technologies instead of using FPGA. c) Software Overview This paper capitalizes on the digital phenomenon; therefore software design draws most of the attention. The VHDL software interface used in this design reduces the complexity and also provides a graphic presentation of the system. The key advantage of VHDL when used for systems design is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires). This software not only compiles the given VHDL code but also produces waveform results. Graphical blocks, chip design and planner are the advanced options available and are used in the software mentioned. Altera's Quartus II and Xilinx webpack are few of the sophisticated Computer Aided Design (CAD) tools to perform the compilation and simulation of any logic circuit design. 
\section[{d) Hardware Overview}]{d) Hardware Overview}\par
The fundamental building block of ALU is shown in Fig.  {\ref 3}. Here bold dots (dip switches) indicate the inputs to an ALU which are selected by the user. The input can either be 1 or 0 indicating 5V and 0 V respectively. A LCD is used to display 16 bit output, whereas * indicates LEDs which are used to show the status of carry out, overflow, borrow and zero. The VHDL code which implies the hardware part of ALU is downloaded on FPGA processor using JTAG cable interfacing PC and the hardware element.\par
A final point is that when a VHDL model is translated into the "gates and wires" that are mapped onto a programmable logic device such as a CPLD or FPGA, and then it is the actual hardware being configured, rather than the VHDL code being "executed" as if on some form of a processor chip. 
\section[{IV. METHODOLOGY}]{IV. METHODOLOGY}\par
Strategizing methods are designed by using part by part approach also known as "Divide and Conquer" or "Bit Slice". This approach provides a convenient method of operation and hence smaller blocks can be easily managed with ease as compared to the larger units.  Truth table design is an effective method compiling all those functions that are needed by the user on a single platform. Table  {\ref 1} indicates the combination of five bit control input S[4 down to 0] with their operation and functions that are used in ALU. Arithmetic, Logic and Shifter units are separated in the table.\par
V. 
\section[{MPLEMENTATION}]{MPLEMENTATION}\par
The VHDL coding of this paper design is compiled and simulated using Altera Quartus-II and has been downloaded in FPGA using Xilinx Spartan XC3S100E kit shown in Fig.  {\ref 5}. The data is updated to the kit using two separate select inputs A and B each carrying 8 bits. The function of FPGA is embedded on the kit along with PROM, LCD, LEDs and DIP switches. A Joint Test Action Group (JTAG) interface connects the FPGA chip with PROM and leads to PC through a serial interface. The structure of such a PROM assembly XC10S is shown in Fig.  {\ref 6}.\par
Since FPGA is user programmable, therefore JTAG is of core significance. PROM has several postulates in the shape of data storage and debugging, permanent storage of data, consistency of operation, low cost, high speed and compactness. PROM used in this design of ALU is "XC10S", which is equipped with the inbuilt circuitry to support and store complex functions. It supports both mode of Master and Slave serial Field Programmable Gate Array. In real time application, after the process of compilation and simulation of the VHDL design, the hardware realization is constructed and tested as shown in Fig. \hyperref[fig_5]{7}. Here the 8-bit inputs are given by means of two sets of DIP switches and the 16-bit output can be displayed on a LCD panel and the result can be verified with the simulated output. The status of the flag register is indicated by a series of 8-bit LEDs. The provision of a select switch used in this hardware enables the user to perform the required operation on the FPGA processor.  
\section[{ACHIEVED RESULTS}]{ACHIEVED RESULTS}\par
This paper requires the building and simulation of the VHDL coding using Xilinx or Altera program. Once the program has been developed, it will be burnt on to a FPGA chip with which the required hardware is obtained. Designing and Testing of ALU is achieved by differentiating the system into four blocks, first deals with Arithmetic Aspects while second is concerned with Logical Unit, similarly third and fourth blocks are for Shifter and Rotate Operations respectively. Simulated output of a sample multiplication operation is shown in Fig. \hyperref[fig_6]{8}.  
\section[{CONCLUSION}]{CONCLUSION}\par
In this project, Arithmetic Logic Unit was successfully designed and implemented using Very High Speed Hardware Descriptive Language and Xilinx Spatan-3E Field Programmable Gate Array. All the primary operations of Arithmetic Logic Unit are fabulously done alongside some extra features that provide status of output. Graphical Splitting and Truth Table formation provided a synthesizable system design by separating Arithmetic, Logic, Shifter and Rotator blocks which were integrated in later stages. Design methods involved follows a TOP-DOWN approach in which software design leads the physical and hardware construction. Software section has been realized using Behavioral Model of VHDL. The programming is done Global ( F )\par
for 8 bit lanes of 2 inputs each but system can accommodate up to 6 input channels. The 5 bit control unit holds responsibility for shaping the output of specified operation. Further enhancements can be made on this system by adding more number of inputs with increased number of bit size. Digital Signal Processing (DSP) is being credited with lots of applications from VHDL designs. Advancement in floating point applications of ALU can mutually benefit the two fields.\par
Books:\begin{figure}[htbp]
\noindent\textbf{1}\includegraphics[]{image-2.png}
\caption{\label{fig_0}Fig. 1 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-3.png}
\caption{\label{fig_1}T}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{234}\includegraphics[]{image-4.png}
\caption{\label{fig_2}Fig. 2 :Fig. 3 :Fig. 4 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{1}\includegraphics[]{image-5.png}
\caption{\label{fig_3}Table 1 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{56}\includegraphics[]{image-6.png}
\caption{\label{fig_4}Fig. 5 :Fig. 6 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{7}\includegraphics[]{image-7.png}
\caption{\label{fig_5}Fig. 7 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{8}\includegraphics[]{image-8.png}
\caption{\label{fig_6}Fig. 8 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{} \par 
\begin{longtable}{P{0.4071261682242991\textwidth}P{0.011915887850467289\textwidth}P{0.11121495327102802\textwidth}P{0.29591121495327105\textwidth}P{0.023831775700934577\textwidth}}
\tabcellsep CPU\tabcellsep COMPARATOR\tabcellsep DSP\tabcellsep \\
\multicolumn{2}{l}{Designing ALU Using}\tabcellsep \tabcellsep \multicolumn{2}{l}{Design and Simulation of}\\
VHDL\tabcellsep \tabcellsep \tabcellsep \multicolumn{2}{l}{Arithmetic Functions}\\
\multicolumn{2}{l}{Input and output of 8 and}\tabcellsep \tabcellsep \tabcellsep \\
\multicolumn{2}{l}{16 bits respectively}\tabcellsep \tabcellsep \tabcellsep \\
\multicolumn{2}{l}{All the operations must be done on Single Chip}\tabcellsep \tabcellsep \multicolumn{2}{l}{Design and Simulation of Logic Functions}\\
\multicolumn{2}{l}{Design has to be simulated}\tabcellsep \tabcellsep \tabcellsep \\
\multicolumn{2}{l}{by using Altera/Xilinx and}\tabcellsep \tabcellsep \tabcellsep \\
\multicolumn{2}{l}{tested on FPGA Board}\tabcellsep \tabcellsep \tabcellsep \\
Research\tabcellsep and\tabcellsep Simplified Approach for\tabcellsep Enormous\tabcellsep enhancements\\
Development\tabcellsep \tabcellsep Students in Electronics\tabcellsep \multicolumn{2}{l}{available to work with}\\
\tabcellsep \tabcellsep \tabcellsep \multicolumn{2}{l}{© 2011 Global Journals Inc. (US)}\end{longtable} \par
 
\caption{\label{tab_0}}\end{figure}
 			\footnote{November} 		 		\backmatter  			  				\begin{bibitemlist}{1}
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\bibitem[Zwolinski ()]{b2}\label{b2} 	 		\textit{Digital System Design with VHDL},  		 			Mark Zwolinski 		.  		2000. Prentice Hall.  	 
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\bibitem[Stephen Brown and Zvonko ()]{b0}\label{b0} 	 		\textit{Fundamentals of digital logic with VHDL Design},  		 			B Stephen Brown 		,  		 			V Zvonko 		.  		2005. McGraw Hill International Edition.  	 	 (2nd Edition) 
\bibitem[Kaliamurthy and Muralidharan ()]{b5}\label{b5} 	 		 			S Kaliamurthy 		,  		 			R Muralidharan 		.  		\textit{VHDL Design of FPGA Arithmetic Processor" International Conference on Engineering and ICT},  				2007.  	 
\bibitem[Xilinx Technologies, Xilinx Data Sheet for XC3S100E]{b8}\label{b8} 	 		 \url{http://direct.xilinx.com/bvdocs/publications/ds312.pdf}  		\textit{Xilinx Technologies, Xilinx Data Sheet for XC3S100E},  				 	 
\bibitem[Xilinx Technologies, Xilinx Data Sheet for XCF01S, Date accessed (2007)]{b9}\label{b9} 	 		\textit{Xilinx Technologies, Xilinx Data Sheet for XCF01S, Date accessed},  		 \url{www.datasheetarchive.com}  		June 2007.  	 
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\end{document}
