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\title{Method to Minimize Data Losses in Multi Stage Flip Flop}
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\begin{document}

             \author[1]{N. Suresh  Kumar}

             \affil[1]{  GITAM University}

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\date{\small \em Received: 9 September 2011 Accepted: 30 September 2011 Published: 11 October 2011}

\maketitle


\begin{abstract}
        


In complex digital circuits the clock arrives at next stages before the data pulses  arrives to the next stage. The clock pulse must be inserted to activate the digital circuits at any  stage starting from first stage. But due to unsynchronization between clock pulse and data there  is a chance of miss hitting in the next stages. This leads improper data transmissions in complex  systems. It creates data   losses in transmission. In the present work a gate controlled clock  scheme is proposed to increase data hitting ratio.         

\end{abstract}


\keywords{clock, Synchronization, data propagation, registers, flip flop}

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\let\tabcellsep& 	 	 		 
\section[{INTRODUCTION}]{INTRODUCTION}\par
n light weighted circuits, contain fewer flip flops the problem may not arise. But the circuits with complex logic circuit with large number of flip-flops may face these types of problems. Because the complex logic circuits cause some delay to propagate the data from one flip flop to other flip flop or from one stage to other stage. In the present paper flip flops and delay logics are considered to describe the problem. Delay elements are often added to improve performance of a wavepipelined circuit by reducing the delay difference of the longest and the shortest paths \hyperref[b0]{[1]}. Unfortunately, precise delay elements that realize the exact delay needed is difficult to obtain. Instead simple logic gates are used for delay balancing, thereby providing more feasible and accurate circuit path delay control under the Min/Max delay model. A heuristic is developed to insert a sufficient number of latches into a combinational circuit to achieve a specified clock cycle time. There are already some existing methods effectively working to improve the data quality in terms of accuracy in propagation \hyperref[b1]{[2]}[3][4] \hyperref[b3]{[5]}. T. Feng proposed new wave pipeline design to achieve faster Clock Cycle Timing (CCT) \hyperref[b1]{[2]} than the conventional pipeline methods. The author T Feng4drt wave pipeline can achieve at least a 48\% performance enhancement on clock cycle time compared with the conventional wave pipeline.\par
This paper presents a new design method for combinational circuits with focus on circuit speed optimization. Today's high speed circuit and advanced fabrication technology facing seviour problem from delay uncertainty an extremely important issue in circuit design. The proposed method the speed optimization achieved with better Clock cycle scheme. By this intrinsic advantage of the proposed method over conventional methods, the proposed new scheme can achieve a better clock cycle than conventional methods.\par
The percentage of propagation error can be bringing to minimum level which is almost zero with the enhanced technology. In the conventional pipeline system it is facing problems due to improper synchronization of clock pulses. This is a universal problem in all the digital systems mostly called clock skew. The system clocking must be such that the output data is clocked after the latest data has arrived at the outputs and before the earliest data from the next clock cycle arrives at the outputs. In the present work a new system is proposed in the path of the clock to remove or reduce the clock skew. There are already few methods effectively working on clock skew such as wavepipelining \hyperref[b3]{[5]}[6] and Me-synchronous pipeline [3] methods. The equalization of path delays comes as a new challenge for the design of wave-pipelined systems. Different clock signal paths can have different delays for a variety of reasons \hyperref[b5]{[7]}. Differences in delays of any active buffers within the clock distribution network may cause un-synchronization of data and clock in double buffer method and wave pipeline method. And it is difficult to identify exact delay value without which the pipe line cannot perform 100\% propagation. 
\section[{II.}]{II.} 
\section[{ENHANCED METHOD}]{ENHANCED METHOD}\par
In the present method simple logic gates are used in clock path to achieve higher data rates and accurate data propagation. In the present circuit the clock pulse applied to the next flip flop only when the first flip flop is ready to transmit the data wave to the next flip flop. In the present work an 8bit four stage circuit is built to test the data rates. In simple combinational circuits with little number of latches, the data propagation path is almost equal to the clock propagation path as shown in figure1. The output will follow 100\% with the input. But when the stages increase in the combinational circuit with more logics and latches the propagation length of the data path will be long when compared with clock path as shown in figure2. In this crucial period it is difficult and highly impossible to get exact input data match with the output in conventional circuits.     F l i p F l o p F l i p F l o p F l i p F l o p F l i p F l o p F l i p F l o p F l i p F l o p F l i p F l o p F l i p F l 
\section[{CONCLUSION}]{CONCLUSION}\par
A new clock scheme is implemented for higher data rates. Parallel processing can be done with new clock system. High speed data can be read through the stages by simultaneous operations, fetching and processing through logic circuit. In the circuit the clock skew is almost minimized when compared to old methods. An eight bit four stage combinational circuit is designed to achieve accurate data. \begin{figure}[htbp]
\noindent\textbf{1}\includegraphics[]{image-2.png}
\caption{\label{fig_0}Figure 1 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{2}\includegraphics[]{image-3.png}
\caption{\label{fig_1}Figure 2 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{3}\includegraphics[]{image-4.png}
\caption{\label{fig_2}Figure 3 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{5}\includegraphics[]{image-5.png}
\caption{\label{fig_3}Figure 5 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-6.png}
\caption{\label{figure6}}\end{figure}
 			\footnote{© 2011 Global Journals Inc. (US)} 			\footnote{November} 		 		\backmatter  			 
\subsection[{RESULTS}]{RESULTS}\par
The hardware is tested and simulations are verified in the software Proteus. In the figure  {\ref 5}  So it took one clock pulse to come input pin of the second stage. And the clock pulse clock2 arrives after one clock pulse. So the output appears after one clock pulse after the input appears at second stage. That is the output will appear at second stage after two clock pulses after the first input appear at first stage. At the same time, while the second stage processing the first data wave the first stage receives the second data wave. That means while processing the one data wave the circuit can fetch second data wave. In the same way while the third stage processing the first data and second stage processing the second data wave the first stage will try to fetch the third wave.			 			  				\begin{bibitemlist}{1}
\bibitem[Jabulaninyathi ()]{b3}\label{b3} 	 		\textit{A high performance hybrid wave pipelined linear feedback shift register with skew tolerant clocks},  		 			Jabulaninyathi 		.  		2004. IEEE. p. .  	 
\bibitem[Chang]{b0}\label{b0} 	 		\textit{Delay balancing using latches},  		 			Chuan-Hua Chang 		.  		Ann Arbor. p. .  		 			University of Michigan 		 	 	 (citeseerx.ist.psu.edu/viewdoc/down load?doi=10.1.1.76.6171) 
\bibitem[Suresh (2011)]{b5}\label{b5} 	 		‘Effect of Interrupt Logic on Delay Balancing Circuit’.  		 			K Suresh 		.  	 	 		\textit{International Journal of Computer Applications}  		August 2011. 2011. US. 27  (4)  p. .  	 	 (Global Journals Inc.) 
\bibitem[Cotten ()]{b4}\label{b4} 	 		‘Maximum rate pipelined systems’.  		 			L Cotten 		.  	 	 		\textit{Proc. AFIPS Spring Joint Comput. Conf},  				 (AFIPS Spring Joint Comput. Conf)  		1969.  	 
\bibitem[Feng ()]{b1}\label{b1} 	 		‘REFERENCES RÉFÉRENCES REFERENCIAS 3. Suryanarayana B. Tatapudi, Student Member’.  		 			T Feng 		.  	 	 		\textit{I2MTC 2008 -IEEE International Instrumentation and Measurement Technology Conference},  				 (Victoria, Vancouver Island, Canada)  		May 12-15, 2008. May 2006. IEEE. 53.  	 	 (A Mesychronous high performance digital systems) 
\bibitem[Gay (1994)]{b2}\label{b2} 	 		‘Timing constraints for wave pipelined systems’.  		 			C 		,  		 			Thomas Gay 		.  	 	 		\textit{IEEE transactions on Computer aided design of integrated circuits}  		august 1994. 13  (8)  p. .  	 
\end{bibitemlist}
 			 		 	 
\end{document}
