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\title{Thermal Stress Analysis of BGA Packaging Structure}
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             \author[1]{Tasneem Khan  Shifa}

             \author[2]{Dr. Md. Faruque  Hossain}

             \affil[1]{  }

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\date{\small \em Received: 8 December 2017 Accepted: 1 January 2018 Published: 15 January 2018}

\maketitle


\begin{abstract}
        


In this paper the performance of the ball grid array (BGA) electronic packaging is investigated. The fields of temperature and stress are analyzed for the overall model & for solder balls by finite element method (FEM) using COMSOL Multiphysics 5.2a software to analyze different aspects to improve the reliability & efficiency of integrated chip. The simulation result shows that the maximum value of temperature and thermal stress are 41 degree Celsius & 199MPa respectively. The maximum temperature is obtained on the chip surface and the maximum stress happens on the outside corner of the ball joints. The range analysis shows that the maximum stress increases with the increase of chip thickness, substrate width, ball pitch, CTE but the value of maximum stress decrease with the increase of ball diameter and Poisson?s ratio.

\end{abstract}


\keywords{ball grid array (BGA), finite element method (FEM), thermal stress analysis, simulation}

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\let\tabcellsep& 	 	 		 
\section[{I. Introduction}]{I. Introduction}\par
n recent years, the volume of a new developed electronic device has reduced by more than three orders of magnitude compared with several years ago. Thus, it is very important to research an efficient electronic packaging form to improve the efficiency and reduce the cost \hyperref[b0]{[1]}. The electronic packaging technologies have developed to control a large amount of heat that is generated through the integrated circuit (IC) and match the coefficient of thermal expansion (CTE) between different parts of packaging materials. Among various advanced forms of packaging, ball grid array (BGA) becomes one of the most promising packaging technologies due to its higher efficiency, smaller geometry size, lower cost \hyperref[b1]{[2]}. However, among all the factors leading to the failure of the electronic device, such as vibration, humidity, loading\& temperature affects mostly.\par
Furthermore, because electronic packaging consists of different CTE materials, the thermal stress emerges during the working cycle due to the expansion between adjacent materials which fails the products. Therefore, it is necessary to find appropriate materials combination to lower the thermal stress. To guarantee the stability of integrated chip, the packaging material should have characteristics like strength and stiffness to prevent stress deformation and other features such as high gas tightness, low density, radiation protection Author ? ? : Department of Electronics and Communication Engineering, Khulna University of Engineering \& Technology, Khulna-9203, and Bangladesh. e-mail: tasneemkhanshifa@gmail.com and low Cost \hyperref[b2]{[3]}.\par
A significant number of literatures are published about the BGA packaging. Luo \hyperref[b3]{[4]} developed an analytical thermal resistance network model to calculate mean die temperature of a typical BOA packaging which is demonstrated to be accurate in predicting the temperature distribution. Z. Sauli, V. Retnasamy, R. Vairavan, K. Anwar, and N. Abdullah \hyperref[b4]{[5]} analyzed the stress response of BGA solder with the different material during maximum vertical loading using the simulation method. The results showed that the Normal BGA demonstrated a higher stress response. Q.Gao, K.K. Wang \hyperref[b5]{[6]} studied the thermal field and stress field distribution when chip worked on a given power. The results showed that the influence on the temperature and stress decreased with the increasing heat convection coefficient. K.K. Wang, L. Wang, L. Wang, Y.Z. Wang \hyperref[b6]{[7]} studied the influence of different materials and boundary conditions on the temperature distribution. The results showed that the packaging temperature rose up faster at the beginning of the simulation than that at the end and high convection significantly reduced the maximum temperature. Also, adhesive thickness had an impediment on heat transfer due to the package temperature slightly rose as the thickness of adhesive increases. S.F. Popular \hyperref[b7]{[8]} studied the reliability of flip chip BGA package based on the finite element method (FEM) parametric analysis. L.L. Mercado, V. Sarihan, Y.F. Guo, and Mawer \hyperref[b8]{[9]} applied FEM parametric analysis to study the reliability of flip chip BGA, and the design parameters including solder bump layout, solder bump center to die edge, solder material/geometry, die size as well as substrate size/material. W. Chen \hyperref[b9]{[10]} investigated the test methodology for assessing reliability performance of both single chip BGA\& multiple chips flip-chip BGA on board assemblies. B. Rosner, J. Liu, and Z. Lai \hyperref[b10]{[11]} developed a thermal cycle testing experiment for the flip chip BGA packaging \&a daisy chained test IC was designed for the packaging reliability testing.\par
The fields of temperature and stress are analyzed for the overall model \& for solder balls by finite element method (FEM) by COMSOL Multiphysics 5.2a software. 
\section[{II. Background a) Pin Grid Array}]{II. Background a) Pin Grid Array}\par
Pin grid array (PGA) is a package with one face covered with pins is in a grid pattern. It is placed in a printed circuit board (PCB) and carry out electrical signal between integrated circuit \& printed circuit board (PCB).PGAs are often mounted on printed circuit boards using the through hole method or inserted into a socket \hyperref[b11]{[12]}. 
\section[{b) Ball Grid Array (BGA)}]{b) Ball Grid Array (BGA)}\par
A ball grid array (BGA) came from the Pin grid array (PGA) in which there are pads instead of pins on the bottom of the package and a tiny solder balls stuck to each of the pads. The device is placed on a PCB with copper pads in a pattern that matches the solder balls. The assembly is then heated which melts the balls \& the melted solders hold the package with the circuit board. Then the solder cools down and solidifies\& forms soldered connections between the device and the PCB [13]. 
\section[{III. Experimental Procedure a) Finite Element Method (FEM)}]{III. Experimental Procedure a) Finite Element Method (FEM)}\par
The finite element method (FEM) is the dominant discretization technique in structural mechanics. To deal with a large problem, it subdivides a large problem into smaller, simpler parts that are called finite elements. The simple equations are used to model these finite elements and they are then assembled into a larger system of equations that models the entire problem. 
\section[{b) Geometry Model}]{b) Geometry Model}\par
A typical 3-D model BGA structure with 16 solder joints with the diameter 0.3 mm are placed on the substrate and connect the electronic chip \& one-quarter model is imported into simulation software COMSOL Multiphysics 5.2a to reduce the calculating time. Figure \hyperref[fig_0]{1} shows the model,   In figure  {\ref 4}, it is seen that among all the sixteen ball grids, the ball grid farthest away from the center has the maximum temperature at the top surface and the minimum one at the bottom surface. So, this temperature difference makes it easier to produce defects like fatigue and cracks.\par
Each other \& pre-stress between them was ignored. The following table \hyperref[tab_2]{2} shows the material parameters.\par
The environment temperature is 25 °Cand the power of the chip is 0.2 Watt. The convective heat coefficient between the chip and substrate is 10W/(m\textasciicircum 2.k) \hyperref[b12]{[14]}. The thermal stress analysis is conducted on the base of the thermal results obtained above. 
\section[{IV. Simulation \& Result Analysis a) Temperature Field}]{IV. Simulation \& Result Analysis a) Temperature Field}\par
Figure  {\ref 3} shows the temperature distribution of BGA model. It indicates that the maximum temperature temperature is on the substrate. The heat generated by the chip transfers to the substrate via the solder joints. Also, the heat also dissipates to the surrounding environment. Finally, a steady state is found.\par
is on the surface of the chip and the minimum Figure  {\ref 5} shows the temperature distribution of the substrate,  From figure  {\ref 6}, the maximum stress happens on the outside corner of the ball joints because of heat dissipation. From Figure \hyperref[fig_3]{7}, the solder joints have the highest stress value due to the higher thermal expansion coefficient than the substrate \& the chip and the maximum \& highest displacement of the solder joints happens in the same place with the maximum stress \hyperref[b12]{[14]}.\par
The maximum value of temperature and thermal stress are 41 degree Celsius \& 199MPa respectively. 
\section[{V. Factors Influencing Thermal Stress}]{V. Factors Influencing Thermal Stress}\par
Maximum stress plays a significant role in affecting the reliability and efficiency of BGA packaging. Various factors were considered for optimization.  In future work, by using these different factors, a standard BGA model can be designed where maximum stress can be lowered and also can be more reliable and efficient. 
\section[{a) Influence of Ball Pitch}]{a) Influence of Ball Pitch}\begin{figure}[htbp]
\noindent\textbf{1}\includegraphics[]{image-2.png}
\caption{\label{fig_0}Figure 1 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{34}\includegraphics[]{image-3.png}
\caption{\label{fig_1}Figure 3 :Figure 4 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{56}\includegraphics[]{image-4.png}
\caption{\label{fig_2}Figure 5 :Figure 6 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{7}\includegraphics[]{image-5.png}
\caption{\label{fig_3}Figure 7 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{891011}\includegraphics[]{image-6.png}
\caption{\label{fig_4}Figure 8 :Figure 9 :Figure 10 :Figure 11 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{1} \par 
\begin{longtable}{}
\end{longtable} \par
 
\caption{\label{tab_0}Table 1}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{1} \par 
\begin{longtable}{P{0.4391666666666667\textwidth}P{0.41083333333333333\textwidth}}
Component\tabcellsep Size (mm)\\
Chip\tabcellsep 8×8×0.65\\
Ball Grid\tabcellsep 0.3\\
Substrate\tabcellsep 10×10×1.5\end{longtable} \par
  {\small\itshape [Note: c) MeshingThe BGA model meshed with 7318 number of domain elements shown below,Figure 2: The mesh result of the BGA model d) Chosen Material \& Parameters]} 
\caption{\label{tab_1}Table 1 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{2} \par 
\begin{longtable}{P{0.425\textwidth}P{0.10793650793650793\textwidth}P{0.16190476190476188\textwidth}P{0.15515873015873013\textwidth}}
Component\tabcellsep Chip\tabcellsep Ball grid\tabcellsep Substrate\\
Material\tabcellsep Si\tabcellsep Sn-Pb\tabcellsep Epoxy\\
Thermal Conductivity (W/m.K)\tabcellsep 120\tabcellsep 30\tabcellsep 0.2\\
CTE\tabcellsep 2.6\tabcellsep 24.5\tabcellsep 18\\
Poisson's ratio\tabcellsep 0.28\tabcellsep 0.35\tabcellsep 0.38\end{longtable} \par
 
\caption{\label{tab_2}Table 2 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{3} \par 
\begin{longtable}{P{0.1297266514806378\textwidth}P{0.0387243735763098\textwidth}P{0.07551252847380409\textwidth}P{0.015489749430523917\textwidth}P{0.029043280182232345\textwidth}P{0.048405466970387244\textwidth}P{0.23428246013667425\textwidth}P{0.007744874715261959\textwidth}P{0.0929384965831435\textwidth}P{0.02710706150341686\textwidth}P{0.15102505694760818\textwidth}}
Stress (MPa)\tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \\
Max.\tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \\
\tabcellsep \tabcellsep \tabcellsep \tabcellsep 55\tabcellsep 0.65\tabcellsep 0.75\tabcellsep 0.85\tabcellsep 0.95\tabcellsep 1.05\\
\tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \multicolumn{2}{l}{Ball Pitch (mm)}\\
\multicolumn{2}{l}{Max. Stress (MPa)}\tabcellsep \multicolumn{2}{l}{170 180 190 200 210}\tabcellsep 179 0.55\tabcellsep 190 0.65\tabcellsep \multicolumn{2}{l}{194 0.75 Chip Thickness (mm) 197 0.85}\tabcellsep 203 0.95\tabcellsep 1.05\tabcellsep XVIII Issue III Version I\\
\multicolumn{2}{l}{Max. Stress (MPa)}\tabcellsep \multicolumn{2}{l}{0 50 100 150 200 250}\tabcellsep 145 8\tabcellsep 170 9\tabcellsep \multicolumn{2}{l}{190 10 Substrate Width (mm) 197 11}\tabcellsep 201 12\tabcellsep 13\tabcellsep Journal of Researches in Engineering ( ) Volume\\
Max. Stress (MPa)\tabcellsep \multicolumn{2}{l}{0 50 100 150 200 250}\tabcellsep \multicolumn{2}{l}{205 0.22}\tabcellsep 198 0.27\tabcellsep \multicolumn{2}{l}{190 Ball Diameter (mm) 156 0.32}\tabcellsep 145 0.37\tabcellsep 0.42\tabcellsep Global\\
\tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep © 2018 Global Journals\end{longtable} \par
 
\caption{\label{tab_3}Table 3 :}\end{figure}
 			\footnote{© 2018 Global Journals} 		 		\backmatter  			  				\begin{bibitemlist}{1}
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\bibitem[Mechanical analysis of ball grid array packages]{b2}\label{b2} 	 		\textit{Mechanical analysis of ball grid array packages},  		 \url{https://seelio.com/w/1vb4/mechanical-analysis-of-ball-grid-array-packages-using-different-solder-ball-materials}  		 	 
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\bibitem[Rosner et al. ()]{b10}\label{b10} 	 		 			B Rosner 		,  		 			J Liu 		,  		 			Z Lai 		.  		\textit{Flip Chip Bonding Using Conductive Adhesives Electronic Components and Technology Conference},  				 (USA)  		1996. p. .  	 
\bibitem[Wang et al. ()]{b6}\label{b6} 	 		‘State analysis of temperature field of electronic package with power chip’.  		 			K K Wang 		,  		 			L Wang 		,  		 			L Wang 		,  		 			Y Z Wang 		.  	 	 		\textit{International Conference on Electronic Packaging Technology},  				 (Dalian)  		2013.  	 
\bibitem[Gao and Wang ()]{b5}\label{b5} 	 		‘Study of the Thermal Field and Thermal Stress Field of Typical BGA Packaging by Numerical Simulation’.  		 			Q Gao 		,  		 			K K Wang 		.  	 	 		\textit{International Conference on Electronic Packaging Technology},  				 (Chengdu)  		2014.  	 
\end{bibitemlist}
 			 		 	 
\end{document}
