\documentclass[11pt,twoside]{article}\makeatletter

\IfFileExists{xcolor.sty}%
  {\RequirePackage{xcolor}}%
  {\RequirePackage{color}}
\usepackage{colortbl}
\usepackage{wrapfig}
\usepackage{ifxetex}
\ifxetex
  \usepackage{fontspec}
  \usepackage{xunicode}
  \catcode`⃥=\active \def⃥{\textbackslash}
  \catcode`❴=\active \def❴{\{}
  \catcode`❵=\active \def❵{\}}
  \def\textJapanese{\fontspec{Noto Sans CJK JP}}
  \def\textChinese{\fontspec{Noto Sans CJK SC}}
  \def\textKorean{\fontspec{Noto Sans CJK KR}}
  \setmonofont{DejaVu Sans Mono}
  
\else
  \IfFileExists{utf8x.def}%
   {\usepackage[utf8x]{inputenc}
      \PrerenderUnicode{–}
    }%
   {\usepackage[utf8]{inputenc}}
  \usepackage[english]{babel}
  \usepackage[T1]{fontenc}
  \usepackage{float}
  \usepackage[]{ucs}
  \uc@dclc{8421}{default}{\textbackslash }
  \uc@dclc{10100}{default}{\{}
  \uc@dclc{10101}{default}{\}}
  \uc@dclc{8491}{default}{\AA{}}
  \uc@dclc{8239}{default}{\,}
  \uc@dclc{20154}{default}{ }
  \uc@dclc{10148}{default}{>}
  \def\textschwa{\rotatebox{-90}{e}}
  \def\textJapanese{}
  \def\textChinese{}
  \IfFileExists{tipa.sty}{\usepackage{tipa}}{}
\fi
\def\exampleFont{\ttfamily\small}
\DeclareTextSymbol{\textpi}{OML}{25}
\usepackage{relsize}
\RequirePackage{array}
\def\@testpach{\@chclass
 \ifnum \@lastchclass=6 \@ne \@chnum \@ne \else
  \ifnum \@lastchclass=7 5 \else
   \ifnum \@lastchclass=8 \tw@ \else
    \ifnum \@lastchclass=9 \thr@@
   \else \z@
   \ifnum \@lastchclass = 10 \else
   \edef\@nextchar{\expandafter\string\@nextchar}%
   \@chnum
   \if \@nextchar c\z@ \else
    \if \@nextchar l\@ne \else
     \if \@nextchar r\tw@ \else
   \z@ \@chclass
   \if\@nextchar |\@ne \else
    \if \@nextchar !6 \else
     \if \@nextchar @7 \else
      \if \@nextchar (8 \else
       \if \@nextchar )9 \else
  10
  \@chnum
  \if \@nextchar m\thr@@\else
   \if \@nextchar p4 \else
    \if \@nextchar b5 \else
   \z@ \@chclass \z@ \@preamerr \z@ \fi \fi \fi \fi
   \fi \fi  \fi  \fi  \fi  \fi  \fi \fi \fi \fi \fi \fi}
\gdef\arraybackslash{\let\\=\@arraycr}
\def\@textsubscript#1{{\m@th\ensuremath{_{\mbox{\fontsize\sf@size\z@#1}}}}}
\def\Panel#1#2#3#4{\multicolumn{#3}{){\columncolor{#2}}#4}{#1}}
\def\abbr{}
\def\corr{}
\def\expan{}
\def\gap{}
\def\orig{}
\def\reg{}
\def\ref{}
\def\sic{}
\def\persName{}\def\name{}
\def\placeName{}
\def\orgName{}
\def\textcal#1{{\fontspec{Lucida Calligraphy}#1}}
\def\textgothic#1{{\fontspec{Lucida Blackletter}#1}}
\def\textlarge#1{{\large #1}}
\def\textoverbar#1{\ensuremath{\overline{#1}}}
\def\textquoted#1{‘#1’}
\def\textsmall#1{{\small #1}}
\def\textsubscript#1{\@textsubscript{\selectfont#1}}
\def\textxi{\ensuremath{\xi}}
\def\titlem{\itshape}
\newenvironment{biblfree}{}{\ifvmode\par\fi }
\newenvironment{bibl}{}{}
\newenvironment{byline}{\vskip6pt\itshape\fontsize{16pt}{18pt}\selectfont}{\par }
\newenvironment{citbibl}{}{\ifvmode\par\fi }
\newenvironment{docAuthor}{\ifvmode\vskip4pt\fontsize{16pt}{18pt}\selectfont\fi\itshape}{\ifvmode\par\fi }
\newenvironment{docDate}{}{\ifvmode\par\fi }
\newenvironment{docImprint}{\vskip 6pt}{\ifvmode\par\fi }
\newenvironment{docTitle}{\vskip6pt\bfseries\fontsize{22pt}{25pt}\selectfont}{\par }
\newenvironment{msHead}{\vskip 6pt}{\par}
\newenvironment{msItem}{\vskip 6pt}{\par}
\newenvironment{rubric}{}{}
\newenvironment{titlePart}{}{\par }

\newcolumntype{L}[1]{){\raggedright\arraybackslash}p{#1}}
\newcolumntype{C}[1]{){\centering\arraybackslash}p{#1}}
\newcolumntype{R}[1]{){\raggedleft\arraybackslash}p{#1}}
\newcolumntype{P}[1]{){\arraybackslash}p{#1}}
\newcolumntype{B}[1]{){\arraybackslash}b{#1}}
\newcolumntype{M}[1]{){\arraybackslash}m{#1}}
\definecolor{label}{gray}{0.75}
\def\unusedattribute#1{\sout{\textcolor{label}{#1}}}
\DeclareRobustCommand*{\xref}{\hyper@normalise\xref@}
\def\xref@#1#2{\hyper@linkurl{#2}{#1}}
\begingroup
\catcode`\_=\active
\gdef_#1{\ensuremath{\sb{\mathrm{#1}}}}
\endgroup
\mathcode`\_=\string"8000
\catcode`\_=12\relax

\usepackage[a4paper,twoside,lmargin=1in,rmargin=1in,tmargin=1in,bmargin=1in,marginparwidth=0.75in]{geometry}
\usepackage{framed}

\definecolor{shadecolor}{gray}{0.95}
\usepackage{longtable}
\usepackage[normalem]{ulem}
\usepackage{fancyvrb}
\usepackage{fancyhdr}
\usepackage{graphicx}
\usepackage{marginnote}

\renewcommand{\@cite}[1]{#1}


\renewcommand*{\marginfont}{\itshape\footnotesize}

\def\Gin@extensions{.pdf,.png,.jpg,.mps,.tif}

  \pagestyle{fancy}

\usepackage[pdftitle={Robustness Evaluation Study of Power RF LDMOS Devices after Thermal Life Tests},
 pdfauthor={}]{hyperref}
\hyperbaseurl{}

	 \paperwidth210mm
	 \paperheight297mm
              
\def\@pnumwidth{1.55em}
\def\@tocrmarg {2.55em}
\def\@dotsep{4.5}
\setcounter{tocdepth}{3}
\clubpenalty=8000
\emergencystretch 3em
\hbadness=4000
\hyphenpenalty=400
\pretolerance=750
\tolerance=2000
\vbadness=4000
\widowpenalty=10000

\renewcommand\section{\@startsection {section}{1}{\z@}%
     {-1.75ex \@plus -0.5ex \@minus -.2ex}%
     {0.5ex \@plus .2ex}%
     {\reset@font\Large\bfseries}}
\renewcommand\subsection{\@startsection{subsection}{2}{\z@}%
     {-1.75ex\@plus -0.5ex \@minus- .2ex}%
     {0.5ex \@plus .2ex}%
     {\reset@font\Large}}
\renewcommand\subsubsection{\@startsection{subsubsection}{3}{\z@}%
     {-1.5ex\@plus -0.35ex \@minus -.2ex}%
     {0.5ex \@plus .2ex}%
     {\reset@font\large}}
\renewcommand\paragraph{\@startsection{paragraph}{4}{\z@}%
     {-1ex \@plus-0.35ex \@minus -0.2ex}%
     {0.5ex \@plus .2ex}%
     {\reset@font\normalsize}}
\renewcommand\subparagraph{\@startsection{subparagraph}{5}{\parindent}%
     {1.5ex \@plus1ex \@minus .2ex}%
     {-1em}%
     {\reset@font\normalsize\bfseries}}


\def\l@section#1#2{\addpenalty{\@secpenalty} \addvspace{1.0em plus 1pt}
 \@tempdima 1.5em \begingroup
 \parindent \z@ \rightskip \@pnumwidth 
 \parfillskip -\@pnumwidth 
 \bfseries \leavevmode #1\hfil \hbox to\@pnumwidth{\hss #2}\par
 \endgroup}
\def\l@subsection{\@dottedtocline{2}{1.5em}{2.3em}}
\def\l@subsubsection{\@dottedtocline{3}{3.8em}{3.2em}}
\def\l@paragraph{\@dottedtocline{4}{7.0em}{4.1em}}
\def\l@subparagraph{\@dottedtocline{5}{10em}{5em}}
\@ifundefined{c@section}{\newcounter{section}}{}
\@ifundefined{c@chapter}{\newcounter{chapter}}{}
\newif\if@mainmatter 
\@mainmattertrue
\def\chaptername{Chapter}
\def\frontmatter{%
  \pagenumbering{roman}
  \def\thechapter{\@roman\c@chapter}
  \def\theHchapter{\roman{chapter}}
  \def\thesection{\@roman\c@section}
  \def\theHsection{\roman{section}}
  \def\@chapapp{}%
}
\def\mainmatter{%
  \cleardoublepage
  \def\thechapter{\@arabic\c@chapter}
  \setcounter{chapter}{0}
  \setcounter{section}{0}
  \pagenumbering{arabic}
  \setcounter{secnumdepth}{6}
  \def\@chapapp{\chaptername}%
  \def\theHchapter{\arabic{chapter}}
  \def\thesection{\@arabic\c@section}
  \def\theHsection{\arabic{section}}
}
\def\backmatter{%
  \cleardoublepage
  \setcounter{chapter}{0}
  \setcounter{section}{0}
  \setcounter{secnumdepth}{2}
  \def\@chapapp{\appendixname}%
  \def\thechapter{\@Alph\c@chapter}
  \def\theHchapter{\Alph{chapter}}
  \appendix
}
\newenvironment{bibitemlist}[1]{%
   \list{\@biblabel{\@arabic\c@enumiv}}%
       {\settowidth\labelwidth{\@biblabel{#1}}%
        \leftmargin\labelwidth
        \advance\leftmargin\labelsep
        \@openbib@code
        \usecounter{enumiv}%
        \let\p@enumiv\@empty
        \renewcommand\theenumiv{\@arabic\c@enumiv}%
	}%
  \sloppy
  \clubpenalty4000
  \@clubpenalty \clubpenalty
  \widowpenalty4000%
  \sfcode`\.\@m}%
  {\def\@noitemerr
    {\@latex@warning{Empty `bibitemlist' environment}}%
    \endlist}

\def\tableofcontents{\section*{\contentsname}\@starttoc{toc}}
\parskip0pt
\parindent1em
\def\Panel#1#2#3#4{\multicolumn{#3}{){\columncolor{#2}}#4}{#1}}
\newenvironment{reflist}{%
  \begin{raggedright}\begin{list}{}
  {%
   \setlength{\topsep}{0pt}%
   \setlength{\rightmargin}{0.25in}%
   \setlength{\itemsep}{0pt}%
   \setlength{\itemindent}{0pt}%
   \setlength{\parskip}{0pt}%
   \setlength{\parsep}{2pt}%
   \def\makelabel##1{\itshape ##1}}%
  }
  {\end{list}\end{raggedright}}
\newenvironment{sansreflist}{%
  \begin{raggedright}\begin{list}{}
  {%
   \setlength{\topsep}{0pt}%
   \setlength{\rightmargin}{0.25in}%
   \setlength{\itemindent}{0pt}%
   \setlength{\parskip}{0pt}%
   \setlength{\itemsep}{0pt}%
   \setlength{\parsep}{2pt}%
   \def\makelabel##1{\upshape ##1}}%
  }
  {\end{list}\end{raggedright}}
\newenvironment{specHead}[2]%
 {\vspace{20pt}\hrule\vspace{10pt}%
  \phantomsection\label{#1}\markright{#2}%

  \pdfbookmark[2]{#2}{#1}%
  \hspace{-0.75in}{\bfseries\fontsize{16pt}{18pt}\selectfont#2}%
  }{}
      \def\TheFullDate{2017-01-15 (revised: 15 January 2017)}
\def\TheID{\makeatother }
\def\TheDate{2017-01-15}
\title{Robustness Evaluation Study of Power RF LDMOS Devices after Thermal Life Tests}
\author{}\makeatletter 
\makeatletter
\newcommand*{\cleartoleftpage}{%
  \clearpage
    \if@twoside
    \ifodd\c@page
      \hbox{}\newpage
      \if@twocolumn
        \hbox{}\newpage
      \fi
    \fi
  \fi
}
\makeatother
\makeatletter
\thispagestyle{empty}
\markright{\@title}\markboth{\@title}{\@author}
\renewcommand\small{\@setfontsize\small{9pt}{11pt}\abovedisplayskip 8.5\p@ plus3\p@ minus4\p@
\belowdisplayskip \abovedisplayskip
\abovedisplayshortskip \z@ plus2\p@
\belowdisplayshortskip 4\p@ plus2\p@ minus2\p@
\def\@listi{\leftmargin\leftmargini
               \topsep 2\p@ plus1\p@ minus1\p@
               \parsep 2\p@ plus\p@ minus\p@
               \itemsep 1pt}
}
\makeatother
\fvset{frame=single,numberblanklines=false,xleftmargin=5mm,xrightmargin=5mm}
\fancyhf{} 
\setlength{\headheight}{14pt}
\fancyhead[LE]{\bfseries\leftmark} 
\fancyhead[RO]{\bfseries\rightmark} 
\fancyfoot[RO]{}
\fancyfoot[CO]{\thepage}
\fancyfoot[LO]{\TheID}
\fancyfoot[LE]{}
\fancyfoot[CE]{\thepage}
\fancyfoot[RE]{\TheID}
\hypersetup{citebordercolor=0.75 0.75 0.75,linkbordercolor=0.75 0.75 0.75,urlbordercolor=0.75 0.75 0.75,bookmarksnumbered=true}
\fancypagestyle{plain}{\fancyhead{}\renewcommand{\headrulewidth}{0pt}}

\date{}
\usepackage{authblk}

\providecommand{\keywords}[1]
{
\footnotesize
  \textbf{\textit{Index terms---}} #1
}

\usepackage{graphicx,xcolor}
\definecolor{GJBlue}{HTML}{273B81}
\definecolor{GJLightBlue}{HTML}{0A9DD9}
\definecolor{GJMediumGrey}{HTML}{6D6E70}
\definecolor{GJLightGrey}{HTML}{929497} 

\renewenvironment{abstract}{%
   \setlength{\parindent}{0pt}\raggedright
   \textcolor{GJMediumGrey}{\rule{\textwidth}{2pt}}
   \vskip16pt
   \textcolor{GJBlue}{\large\bfseries\abstractname\space}
}{%   
   \vskip8pt
   \textcolor{GJMediumGrey}{\rule{\textwidth}{2pt}}
   \vskip16pt
}

\usepackage[absolute,overlay]{textpos}

\makeatother 
      \usepackage{lineno}
      \linenumbers
      
\begin{document}

             \author[1]{M.  Masmoudi}

             \affil[1]{  LATIS-ENISo, 4023 Sousse University, Tunisia}

\renewcommand\Authands{ and }

\date{\small \em Received: 6 December 2016 Accepted: 2 January 2017 Published: 15 January 2017}

\maketitle


\begin{abstract}
        


This paper presents a synthesis of robustness evaluation on power RF LDMOS devices and its relation with electrical and physical behaviours after RF life-tests. It is important to understand the physical degradation mechanism effects and the liaison on drifts of critical electrical parameters after life ageing tests, in I-V such as threshold voltage (V th ), the feedback capacitance (C rss ) in C-V and the S-parameter (S 21 ) in RF. It shows with tracking of set parameters that Hot Carrier Injection (HCI) phenomenon appears. It is the main cause for device degradation leading to the interface state generation (traps), which results in a build up of negative charge at Si/SiO 2 interface. More interface states are created due to a located maximum impact ionization rate at the gate edge. Such simulations correctly take into account interactions coupled between electrical, thermal and RF behaviours in device inside using the FEM method. A numerical model (Silvaco-Atlas) was used to confirm degradation phenomena. The problem of hot-electron should be taken into consideration in the design of the power RF MOS devices and can be a useful tool to investigate reliability in MOSFET.

\end{abstract}


\keywords{}

\begin{textblock*}{18cm}(1cm,1cm) % {block width} (coords) 
\textcolor{GJBlue}{\LARGE Global Journals \LaTeX\ JournalKaleidoscope\texttrademark}
\end{textblock*}

\begin{textblock*}{18cm}(1.4cm,1.5cm) % {block width} (coords) 
\textcolor{GJBlue}{\footnotesize \\ Artificial Intelligence formulated this projection for compatibility purposes from the original article published at Global Journals. However, this technology is currently in beta. \emph{Therefore, kindly ignore odd layouts, missed formulae, text, tables, or figures.}}
\end{textblock*}


\let\tabcellsep& 	 	 		 
\section[{Introduction}]{Introduction}\par
ateral diffused metal-oxide-semiconductor (LDMOS) have been widely used in many smart power applications. Also on base stations, TV broadcast or in radar applications with high capabilities particularly in terms of RF, output power and Power Added Efficiency (PAE). These applications can cause damage and limiting factors to device reliability, especially to the gate oxide of MOS devices \hyperref[b0]{[1,}\hyperref[b1]{2,}\hyperref[b2]{3]}. Quite often accelerated life tests of MOS capacitors are performed by applying a high constant voltage at the gate contact (constant voltage stress: CVS) or by injecting a constant current across the oxide (constant current stress: CCS) over a period of time. They produce electrical instabilities which have been the subject of numerous experimental studies in MOS devices \hyperref[b3]{[4,}\hyperref[b4]{5]}. Current is a more effective parameter than voltage for defect detection in MOSFET devices and CMOS ICs, although both are necessary for complete testing.\par
Problems related to oxide degradation are of increasing concern for the development of MOS technology. The leakage current represents one of the most important issues of oxide reliability, especially for MOS applications \hyperref[b5]{[6]}. The leakage current with temperature can contribute to the thermal runaway of device \hyperref[b6]{[7]}. Many papers have been devoted to the study of leakage current and its relation with device lifetime \hyperref[b5]{[6,}\hyperref[b7]{8]}. Leakage current in a MOSFET can be a significant contributor to power dissipation \hyperref[b8]{[9]}. A small amount of leakage current is always present, even in healthy devices. The maximum allowable leakage current in a MOSFET is the manufacturer specified zero-gatevoltage drain current (I DSS ) and gate body leakage current (I GSS ). I DSS is the current flowing between the drain and the source when the gate and source are at the same potential. I GSS is the current flowing between the gate and the source when the source and drain are at the same potential.\par
An electrical stress can produce an increase of the low field leakage current across thin gate oxides, further reducing the lifetime of devices \hyperref[b7]{[8]}. Failures that are precipitated by excessive leakage currents include junction and dielectric failures \hyperref[b8]{[9]}. Which consist of leakage through the oxide layer leading to destruction of the dielectric film. Therefore, the leakage current can reach the semiconductor surface and may lead to degradation of the electrical properties of the transistor \hyperref[b8]{[9]}. It is required to study the hot electron induced performance degradation of MOS transistors. In order to qualify new power RF LDMOS reliability for radar applications, a 3000 h pulsed RF life test has been conducted on a dedicated RF S-band test bench in operating modes \hyperref[b10]{[11]}.\par
This work presents a degradation study to the properties and various mechanisms of thin gate oxides, based on the electric characterization of leakage current increase on power MOSFET transistor behaviour after new experimental accelerated ageing tests under various conditions. The content of this paper is presented as follows: the section 2 describes the life test bench and the general power RF LDMOS transistor performances. The discussion of simulation and experimental results are shown in Section 3. The conclusion and prospects are given in Section 4. 
\section[{II. Experimental Setup Of Ageing Test}]{II. Experimental Setup Of Ageing Test}\par
Bench And Simulation Process and implemented an innovative reliability bench able to keep track of all RF powers, voltages and device baseplate temperatures whose values correspond to stress operating conditions \hyperref[b13]{[14]}. This bench is able to keep track many parameters like voltages, currents, base-plate temperature, and peak power. Eight devices is the bench capacity to be tested simultaneously in order to keep it easy to manage. The Fig.  {\ref 1} and Fig.  {\ref 2} represent the component under test placed on its test fixture, supplied by DC power and connected to RF connector (type N). The conditions of pulsed RF life test are much closed of radars applications with operating 24h/24h.\par
The bench consists of three interdependent subsets: * a microwave part, * a control/command part piloted by PC, * thermal module for each devices.\par
The microwave part essentially allows the power injection and measurement in every branch for each device. Each branch contains a tuner to set precise output VSWR stress on any of the devices. The command/control system ensures the achievement of the following functions: * biasing voltage supply and current measurement tracking, * separate control and measurement of each device temperature, * power switching between the eight devices branches, * safe data record. * The measured data on each branch are the following: * input, output and reflected power, * output power variation in RF pulse , * device biasing current, * temperature.\par
All data necessary to keep track of each device degradation evolution in real time are secured thanks to the rack. Life-tests are run in the working conditions (pulsed RF) using various device base plate temperatures (10°C, and 150°C) and a high drainsource voltage (44 V) in order to get more power from the device for radar applications.\par
The RF transistors (8 samples) have been submitted during 3000 hours to ageing test on the reliability bench. This bench operates in radiofrequency pulse mode. During the life test, the goal is to study the component performances in actual working situation to ensure that it will maintain a good performance level. The device under test is placed on a thermal module in order to maintain a constant flange temperature. The command unit manages DC supply voltage, temperature regulation and RF signal monitoring.\par
The picture of 50?-matched test fixture on thermal support using the Peltier effect for power LDMOS amplifier in S-band radar application.\par
The component is in centre of support of test specifically designed for operation at full power in pulsed mode (2.9 GHz and 44 V). These values (frequency and tension) are particularly high compared to nominal values given by the manufacturer (2.2 GHz under 26 V). The power RF-LDMOS device under test is a commercial telecom dedicated transistor (encapsulated in a 2-lead flange package with a ceramic cap) S-band operating in class B at saturation and 65 V DC biasing. Indeed, these performances are given in conditions of width pulse 500 ?s with a duty cycle of 50\%. The gate length is equal to 0.8µm.\par
The Power density is equal to 1.89 W/mm. More than 61\% of drain efficiency, and a gain More than of 11 dB can be obtained around the S band frequency at 2200 MHz in a common source test circuit. The junction temperature does not exceed 150° C for a flange temperature equal to 65° C. The thermal resistance is 0.2 C/W.\par
A modified structure of RF power N channel LDMOS, previously developed by Raman et al \hyperref[b14]{[15]}, was implemented and simulated using the physical simulator Atlas of Silvaco \hyperref[b15]{[16]}. Fig.  {\ref 3} shows the device's structure with approximate doping wells. The main geometrical and technological parameters are given in Table \hyperref[tab_0]{1}. The implemented structure is typically similar to our tested device. Consequently the qualitative understanding of physical phenomenon will be studied. The suggested structure has a Gaussian doping profile along LDD and channel surface. The doping profile was optimized using a technological process simulation carried out by SSUPREM3 \hyperref[b15]{[16]}, see Fig.  {\ref 3}. 
\section[{III.}]{III.} 
\section[{Results And Discussion}]{Results And Discussion}\par
The bench allows to record temperature, currents and voltages (gate and drain), the input power, reflective and output powers. After RF life-tests, the degraded device under test was characterized at ambient temperature, and then a parameter set is extracted.\par
The current I ds measured is average and in order to have the correct peak current, the duty cycle is needed on the expression of DE. During all the life tests, threshold voltage V th , drain-source current I ds and feedback capacitance C rss are shifted. We can partially conclude that these three DC critical parameters are affected by the RF life test. The increase of the V th was detected and it presented a good correlation with the I ds slump (decrease of the I ds corresponded to increase of the R ds-on ). The shift after and before life tests of device threshold voltage V th is presented in fig.  {\ref 4}. An interpretation is proposed to explain the discernable change observed on the feedback capacitance, once Fig.  {\ref 6} displays changes of S-parameter (S 21 ) before and after RF life-tests at 10°C and 150°C. The gate-source voltage for S-parameters measurement was 4.7 V, and the drain-source voltage was 28 V. The devices are operated in the saturation region. Ideally the I GSS value would be zero for voltage levels that are less than the voltage required to reach the dielectric strength of the gate oxide. In the data sheet the value is less than 40 nA (Table \hyperref[tab_1]{2}). Fig.  {\ref 7}-a shows the gate leakage current (I GSS ) measured of three samples power RF LDMOS before ageing test.\par
Overstressing the gate either periodically with RF or statically with DC can also cause an increase of I GSS and thus degrades device performance with respect to RF power gain. Fig.  {\ref 7-b} shows the increase Gate leakage current (I GSS ) measured of three samples power RF LDMOS after ageing test but still far from the total limit of device failure. I GSS due to many factors that are related to the integrity of gate oxide and surrounding regions. I GSS can be used to evaluate reliability of this integral component of the MOSFET. Increase of this parameter with a particular device stress can be used to extrapolate the mean time failure (MTTF) of the gate oxide \hyperref[b11]{[12]}. Other considerations for the gate oxide include careful electrostatic-discharge (ESD) precautions since the gate oxide is easily damaged \hyperref[b11]{[12]}.\par
A higher junction temperature will increase the leakage current \hyperref[b8]{[9,}\hyperref[b9]{10]} which may lead to thermal runaway phenomenon \hyperref[b12]{[13]}. The electrical parameters are shown in Table \hyperref[tab_1]{2}, in which the measured and the manufacturer's data sheet values of the power MOSFET are compared.\par
The breakdown voltage as per the manufacturer's data sheet (Vgs=0; I ds =0.2mA) is higher than 75 V. The value of this voltage V (BR)DSS was found 86 V in the case virgin and 81 V after ageing. I DSS include minority carrier injection from the source due to carriers overcoming the energy barrier resulting from surface band bending and also from sub-critical avalanching caused by high electric fields due to a non-ideal body as well as the Laterally-Diffused-Drain (LDD) doping profile \hyperref[b11]{[12]}.\par
After accelerated RF pulsed life test, the degradation of leakage current can be explained by the increase of V th and C rss . These parameters are degraded due to the interface state generation after stress, device performances should be degraded due to the same degradation mechanism. This indicates that the performance degradation is mainly due to the hot carrier induced interface state generation \hyperref[b16]{[17,}\hyperref[b17]{18]}. The Miller capacitance C rss is composed of two parts, the oxide capacitance (C OX ) and the drift region capacitance (C SI ) \hyperref[b18]{[19]}.\par
The electric parameters of MOS transistor are more and more sensitive to defects bound to the presence of charges in the gate oxide and at the Si/SiO 2 interface \hyperref[b9]{[10]}.\par
The origin of the observed shift could be related to the presence of very high electric field, which increases carrier injection into the grown silicon dioxide layer (SiO 2 ) and into interface state Si/SiO 2 \hyperref[b9]{[10,}\hyperref[b18]{19]}. The detail of the lateral electric field distribution of the active silicon layer in channel and drift regions is shown in Fig.  {\ref 8}.\par
The hot carriers produce an additional interface trap density and trapped electron charge which results in a build up of negative charge at Si/SiO 2 interface \hyperref[b19]{[20]}. This negative charge attracts holes depleting the negative charge in the power LDMOS N-drift region and by consequent increasing the R ds-on device resistance. Hence, R ds-on , C rss and I dsat variations are more remarkable at 10°C, due to the fact that the maximum impact ionization rate is located near the gate edge, see Fig.  {\ref 9}.\par
The aggressive gate leakage current due to the carrier direct tunneling has become as ultimate limit for gate oxide down scaling \hyperref[b5]{[6]}. The RF performances are not stable during all 3000 h the life test; we see a variation of I ds . This variation affects the RF performances. According to the literature \hyperref[b18]{[19,}\hyperref[b19]{20]}, the most probable cause of degradation for power RF LDMOS technology is attributed to hot electron-induced interface state generation and/or impact ionization. May be state interface Si/SiO 2 between drain and gate are responsible of this phenomenon. In order to explain this behaviour, the characterisation of these defects should be investigated. Particularly, the distribution of the data in the figures shows that the aging of the transistor is relatively dependent of the temperature.   IV. 
\section[{Conclusions and Prospects}]{Conclusions and Prospects}\par
This objective constitutes an investigation to clarify the problems related of Hot Carrier Injection effects for reliability exerted on RF LDMOS under operating conditions of radar application (stress: electrical, thermal and RF). The reliability is shown by monitoring I ds , V th , C rss , S 21 , T°C and I GSS parameters in order to put in evidence the device performances. The simulation approach helps to assess the device robustness under critical conditions by means of the temperature evaluation, RF and current distributions in LDMOS structures operating. The results obtained highlighted a degradation caused primarily by the mechanism of hot carrier injected in oxide layer and in channel interface states (i.e. hot-electron-induced interface state generation and/or impact ionization), and in turn its effect on critical parameter drifts (I-V, C-V and RF). These are sensitive parameters to the electrons injected in gate/SiO 2 interface traps.\par
This paper represents the starting point for the development of an accurate and more complex FEM based simulation concept which would correctly include electro-thermal effects. Further failure mechanisms, e.g. the possible activation of the CEM will be integrated within the simulation condition. Moreover, it would be interesting to make the connection with the normal life of a component, through an aging model or MTTF (Mean Time To Failure). The comparison of this study with other technologies such as IGBT and VDMOS is underway.\begin{figure}[htbp]
\noindent\textbf{12}\includegraphics[]{image-2.png}
\caption{\label{fig_0}Fig. 1 :Fig. 2 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{32017456789}\includegraphics[]{image-3.png}
\caption{\label{fig_1}Fig. 3 : 2017 FFig . 4 :Fig. 5 :Fig. 6 :CFig. 7 :Fig. 8 :Fig. 9 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{1} \par 
\begin{longtable}{P{0.85\textwidth}}
Year 2017\\
47\\
of Researches in Engineering ( ) Volume XVII Issue VI Version I F\\
Global Journal\end{longtable} \par
 
\caption{\label{tab_0}Table 1 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{2} \par 
\begin{longtable}{P{0.34972752043596733\textwidth}P{0.20844686648501362\textwidth}P{0.0949591280653951\textwidth}P{0.0717983651226158\textwidth}P{0.1250681198910082\textwidth}}
\multicolumn{2}{l}{Parameter}\tabcellsep \multicolumn{3}{l}{Value (µm)}\\
\multicolumn{2}{l}{Source length}\tabcellsep \tabcellsep \multicolumn{2}{l}{1.1}\\
\multicolumn{3}{l}{Source-gate spacing}\tabcellsep 1\tabcellsep \\
\multicolumn{2}{l}{Gate length}\tabcellsep \tabcellsep \multicolumn{2}{l}{0.8}\\
\multicolumn{2}{l}{Gate-drain spacing}\tabcellsep \tabcellsep 3\tabcellsep \\
\multicolumn{2}{l}{Drain length}\tabcellsep \tabcellsep \multicolumn{2}{l}{1.1}\\
\multicolumn{3}{l}{Gate oxide thickness}\tabcellsep \multicolumn{2}{l}{0.065}\\
Parameter measured\tabcellsep \multicolumn{3}{l}{Measured value Degraded Virgin shift\%}\tabcellsep Data sheet value\\
I GSS\tabcellsep 12 pA\tabcellsep 340 pA >100\tabcellsep \tabcellsep ? 40 nA\\
I DSS\tabcellsep 2 nA\tabcellsep 90 nA >100\tabcellsep \tabcellsep ? 1.5 µA\\
V th\tabcellsep 4.1 V\tabcellsep 4.83 V\tabcellsep \multicolumn{2}{l}{17 4v ? ; ? 5v}\\
V (BR)DSS\tabcellsep 86 V\tabcellsep 81 V\tabcellsep 6\tabcellsep 75V ?\\
Crss\tabcellsep \multicolumn{2}{l}{0.43pF 0.34 pF 21}\tabcellsep \tabcellsep typ. 0.5 pF\\
S 21\tabcellsep \multicolumn{2}{l}{-7.3 dB -10 dB 36}\tabcellsep \tabcellsep ? 11 dB\end{longtable} \par
 
\caption{\label{tab_1}Table 2 :}\end{figure}
 			\footnote{© 2017 Global Journals Inc. (US)} 			\footnote{Year 2017 F again more noticeable at 10°C. The C rss at zero drainsource bias is reduced from 2.6pF to 1.8pF at 10 °C, indicating a shift of 30\%. Even at 26V bias, the C rss is reduced from 0.43pF to 0.34pF (shift 21\%), see fig.5.} 			\footnote{Robustness Evaluation Study of Power RF LDMOS Devices after Thermal Life Tests © 2017 Global Journals Inc. (US)} 		 		\backmatter  			  				\begin{bibitemlist}{1}
\bibitem[Latry and Dherbécourt ()]{b0}\label{b0} 	 		\textit{A 5000 h RF life test on 330 W RF-LDMOS transistors for radars applications},  		 			O Latry 		,  		 			P Dherbécourt 		.  		2010. p. .  	 
\bibitem[Raychaudhuri ()]{b9}\label{b9} 	 		‘A simple method to qualify the LDD structure against the early mode of hotcarrier degradation’.  		 			A Raychaudhuri 		.  	 	 		\textit{IEEE Trans. Electron Devices}  		1996. p. .  	 
\bibitem[Atlas User's Manual-Device Simulation Software Silvaco International ()]{b15}\label{b15} 	 		‘Atlas User's Manual-Device Simulation Software’.  	 	 		\textit{Silvaco International},  				 (Santa Clara, California)  		1998.  	 
\bibitem[Yuan and Jiang ()]{b18}\label{b18} 	 		‘Evaluation of hotelectron effect on LDMOS device and circuit performances’.  		 			Jiann-Shiun Yuan 		,  		 			L Jiang 		.  	 	 		\textit{IEEE Trans Electron Dev}  		2008. p. .  	 
\bibitem[Takagi et al. ()]{b7}\label{b7} 	 		‘Experimental evidence of inelastic tunnelling in stress-induced leakage current’.  		 			S Takagi 		,  		 			N Yasuda 		,  		 			A Toriumi 		.  	 	 		\textit{IEEE Trans Electron Dev}  		1999. 46 p. .  	 
\bibitem[Gares et al. ()]{b10}\label{b10} 	 		‘Hot carrier reliability of RF N-LDMOS for S band radar application’.  		 			M Gares 		,  		 			M Masmoudi 		,  		 			P Bertram 		,  		 			J Marcon 		,  		 			M Belaid 		.  	 	 		\textit{M. Reliability}  		2006. 46 p. .  	 
\bibitem[Liu ()]{b16}\label{b16} 	 		‘Hot-Carrier-Induced Linear Drain Current Degradation of LDMOS Under Pulse Gate Stress With Amplitudes’.  		 			S Liu 		.  	 	 		\textit{E. Devi. Letter}  		2013. p. .  	 
\bibitem[Starkov ()]{b2}\label{b2} 	 		‘Local oxide capacitance as crucial parameter for characterization of hot-carrier degradation in n-MOSFETs’.  		 			I Starkov 		.  	 	 		\textit{Journal Vacuum Science Technology B}  		2013. p. .  	 
\bibitem[Corso ()]{b19}\label{b19} 	 		\textit{Measurement of the hot carrier damage profile in LDMOS devices stressed at high drain voltage. Micro. Reliability},  		 			D Corso 		.  		2007. p. .  	 
\bibitem[Li and Schram ()]{b4}\label{b4} 	 		\textit{Mechanism of O 2 -anneal induced Vfb shifts of Ru gated stacks},  		 			Z Li 		,  		 			T Schram 		.  		2007. p. .  	 
\bibitem[Mohammed Aftab Alam ()]{b8}\label{b8} 	 		‘Member Influence of Molding Compound on Leakage Current in MOS Transistors’.  		 			Mohammed Aftab Alam 		.  	 	 		\textit{IEEE Trans on components}  		2011. p. .  	 
\bibitem[Ielmini A and Sottocornola ()]{b5}\label{b5} 	 		\textit{Modeling of stress-induced leakage current and impact ionization in MOS devices},  		 			Daniele Ielmini A 		,  		 			Alessandro Sottocornola 		,  		 			S 		.  		2002. p. .  	 
\bibitem[Dibra et al. ()]{b6}\label{b6} 	 		‘On the Origin of Thermal Runaway in a Trench Power MOSFET’.  		 			Donald Dibra 		,  		 			Matthias Stecher 		,  		 			Stefan Decker 		.  	 	 		\textit{IEEE Trans Electron Dev}  		2011. 58 p. .  	 
\bibitem[Kerber et al. ()]{b3}\label{b3} 	 		‘Origin of the threshold voltage instability in SiO2 /HfO2 dual layer gate dielectrics’.  		 			A Kerber 		,  		 			E Cartier 		,  		 			L Pantisano 		,  		 			R Degraeve 		.  	 	 		\textit{IEEE Electron Dev Lett}  		2003. p. .  	 
\bibitem[John and Hanson ()]{b11}\label{b11} 	 		\textit{Relate LDMOS device parameters to RF performance. STMicroelectronics, Application note: AN 1228},  		 			P John 		,  		 			B Hanson 		.  		2000.  	 
\bibitem[Aritome et al.]{b1}\label{b1} 	 		‘Reliability issues of flash memory cells’.  		 			S Aritome 		,  		 			R Shirota 		,  		 			G Hemink 		.  	 	 		\textit{Proc IEEE 1993},  				 (IEEE 1993)  		p. .  	 
\bibitem[Shuming et al. ()]{b17}\label{b17} 	 		‘RF LDMOS with extreme low parasitic feedback capacitance and high hot-carrier immunity’.  		 			X Shuming 		,  		 			F Pangdow 		,  		 			W Jianqing 		,  		 			Changhong 		.  	 	 		\textit{IE DM}  		1999. p. .  	 
\bibitem[Reggiani et al. ()]{b12}\label{b12} 	 		‘Simulation of Hot-Carrier and Thermal Degradation in STI-LDMOS Transistors, Electron Devices’.  		 			S Reggiani 		,  		 			G Barone 		,  		 			Tcad 		.  	 	 		\textit{IEEE Transactions}  		2013. p. .  	 
\bibitem[Raman et al. ()]{b14}\label{b14} 	 		‘Simulation of nonequilibrium thermal effects in power LDMOS transistors’.  		 			D G Raman 		,  		 			T S Walker 		,  		 			Fisher 		.  	 	 		\textit{Solid-State Electronics}  		2003. p. .  	 
\bibitem[Reggiani and Barone ()]{b13}\label{b13} 	 		‘TCAD Smulation of Hot-Carrier and Thermal Degradation in STI-LDMOS Transistors’.  		 			S Reggiani 		,  		 			Barone 		.  	 	 		\textit{IEEE Transactions Electron Devices}  		2013. p. .  	 
\end{bibitemlist}
 			 		 	 
\end{document}
