\documentclass[11pt,twoside]{article}\makeatletter

\IfFileExists{xcolor.sty}%
  {\RequirePackage{xcolor}}%
  {\RequirePackage{color}}
\usepackage{colortbl}
\usepackage{wrapfig}
\usepackage{ifxetex}
\ifxetex
  \usepackage{fontspec}
  \usepackage{xunicode}
  \catcode`⃥=\active \def⃥{\textbackslash}
  \catcode`❴=\active \def❴{\{}
  \catcode`❵=\active \def❵{\}}
  \def\textJapanese{\fontspec{Noto Sans CJK JP}}
  \def\textChinese{\fontspec{Noto Sans CJK SC}}
  \def\textKorean{\fontspec{Noto Sans CJK KR}}
  \setmonofont{DejaVu Sans Mono}
  
\else
  \IfFileExists{utf8x.def}%
   {\usepackage[utf8x]{inputenc}
      \PrerenderUnicode{–}
    }%
   {\usepackage[utf8]{inputenc}}
  \usepackage[english]{babel}
  \usepackage[T1]{fontenc}
  \usepackage{float}
  \usepackage[]{ucs}
  \uc@dclc{8421}{default}{\textbackslash }
  \uc@dclc{10100}{default}{\{}
  \uc@dclc{10101}{default}{\}}
  \uc@dclc{8491}{default}{\AA{}}
  \uc@dclc{8239}{default}{\,}
  \uc@dclc{20154}{default}{ }
  \uc@dclc{10148}{default}{>}
  \def\textschwa{\rotatebox{-90}{e}}
  \def\textJapanese{}
  \def\textChinese{}
  \IfFileExists{tipa.sty}{\usepackage{tipa}}{}
\fi
\def\exampleFont{\ttfamily\small}
\DeclareTextSymbol{\textpi}{OML}{25}
\usepackage{relsize}
\RequirePackage{array}
\def\@testpach{\@chclass
 \ifnum \@lastchclass=6 \@ne \@chnum \@ne \else
  \ifnum \@lastchclass=7 5 \else
   \ifnum \@lastchclass=8 \tw@ \else
    \ifnum \@lastchclass=9 \thr@@
   \else \z@
   \ifnum \@lastchclass = 10 \else
   \edef\@nextchar{\expandafter\string\@nextchar}%
   \@chnum
   \if \@nextchar c\z@ \else
    \if \@nextchar l\@ne \else
     \if \@nextchar r\tw@ \else
   \z@ \@chclass
   \if\@nextchar |\@ne \else
    \if \@nextchar !6 \else
     \if \@nextchar @7 \else
      \if \@nextchar (8 \else
       \if \@nextchar )9 \else
  10
  \@chnum
  \if \@nextchar m\thr@@\else
   \if \@nextchar p4 \else
    \if \@nextchar b5 \else
   \z@ \@chclass \z@ \@preamerr \z@ \fi \fi \fi \fi
   \fi \fi  \fi  \fi  \fi  \fi  \fi \fi \fi \fi \fi \fi}
\gdef\arraybackslash{\let\\=\@arraycr}
\def\@textsubscript#1{{\m@th\ensuremath{_{\mbox{\fontsize\sf@size\z@#1}}}}}
\def\Panel#1#2#3#4{\multicolumn{#3}{){\columncolor{#2}}#4}{#1}}
\def\abbr{}
\def\corr{}
\def\expan{}
\def\gap{}
\def\orig{}
\def\reg{}
\def\ref{}
\def\sic{}
\def\persName{}\def\name{}
\def\placeName{}
\def\orgName{}
\def\textcal#1{{\fontspec{Lucida Calligraphy}#1}}
\def\textgothic#1{{\fontspec{Lucida Blackletter}#1}}
\def\textlarge#1{{\large #1}}
\def\textoverbar#1{\ensuremath{\overline{#1}}}
\def\textquoted#1{‘#1’}
\def\textsmall#1{{\small #1}}
\def\textsubscript#1{\@textsubscript{\selectfont#1}}
\def\textxi{\ensuremath{\xi}}
\def\titlem{\itshape}
\newenvironment{biblfree}{}{\ifvmode\par\fi }
\newenvironment{bibl}{}{}
\newenvironment{byline}{\vskip6pt\itshape\fontsize{16pt}{18pt}\selectfont}{\par }
\newenvironment{citbibl}{}{\ifvmode\par\fi }
\newenvironment{docAuthor}{\ifvmode\vskip4pt\fontsize{16pt}{18pt}\selectfont\fi\itshape}{\ifvmode\par\fi }
\newenvironment{docDate}{}{\ifvmode\par\fi }
\newenvironment{docImprint}{\vskip 6pt}{\ifvmode\par\fi }
\newenvironment{docTitle}{\vskip6pt\bfseries\fontsize{22pt}{25pt}\selectfont}{\par }
\newenvironment{msHead}{\vskip 6pt}{\par}
\newenvironment{msItem}{\vskip 6pt}{\par}
\newenvironment{rubric}{}{}
\newenvironment{titlePart}{}{\par }

\newcolumntype{L}[1]{){\raggedright\arraybackslash}p{#1}}
\newcolumntype{C}[1]{){\centering\arraybackslash}p{#1}}
\newcolumntype{R}[1]{){\raggedleft\arraybackslash}p{#1}}
\newcolumntype{P}[1]{){\arraybackslash}p{#1}}
\newcolumntype{B}[1]{){\arraybackslash}b{#1}}
\newcolumntype{M}[1]{){\arraybackslash}m{#1}}
\definecolor{label}{gray}{0.75}
\def\unusedattribute#1{\sout{\textcolor{label}{#1}}}
\DeclareRobustCommand*{\xref}{\hyper@normalise\xref@}
\def\xref@#1#2{\hyper@linkurl{#2}{#1}}
\begingroup
\catcode`\_=\active
\gdef_#1{\ensuremath{\sb{\mathrm{#1}}}}
\endgroup
\mathcode`\_=\string"8000
\catcode`\_=12\relax

\usepackage[a4paper,twoside,lmargin=1in,rmargin=1in,tmargin=1in,bmargin=1in,marginparwidth=0.75in]{geometry}
\usepackage{framed}

\definecolor{shadecolor}{gray}{0.95}
\usepackage{longtable}
\usepackage[normalem]{ulem}
\usepackage{fancyvrb}
\usepackage{fancyhdr}
\usepackage{graphicx}
\usepackage{marginnote}

\renewcommand{\@cite}[1]{#1}


\renewcommand*{\marginfont}{\itshape\footnotesize}

\def\Gin@extensions{.pdf,.png,.jpg,.mps,.tif}

  \pagestyle{fancy}

\usepackage[pdftitle={Modelling and Simulation of Microcode based Built-In Self Test Technology for Multiported Memory},
 pdfauthor={}]{hyperref}
\hyperbaseurl{}

	 \paperwidth210mm
	 \paperheight297mm
              
\def\@pnumwidth{1.55em}
\def\@tocrmarg {2.55em}
\def\@dotsep{4.5}
\setcounter{tocdepth}{3}
\clubpenalty=8000
\emergencystretch 3em
\hbadness=4000
\hyphenpenalty=400
\pretolerance=750
\tolerance=2000
\vbadness=4000
\widowpenalty=10000

\renewcommand\section{\@startsection {section}{1}{\z@}%
     {-1.75ex \@plus -0.5ex \@minus -.2ex}%
     {0.5ex \@plus .2ex}%
     {\reset@font\Large\bfseries}}
\renewcommand\subsection{\@startsection{subsection}{2}{\z@}%
     {-1.75ex\@plus -0.5ex \@minus- .2ex}%
     {0.5ex \@plus .2ex}%
     {\reset@font\Large}}
\renewcommand\subsubsection{\@startsection{subsubsection}{3}{\z@}%
     {-1.5ex\@plus -0.35ex \@minus -.2ex}%
     {0.5ex \@plus .2ex}%
     {\reset@font\large}}
\renewcommand\paragraph{\@startsection{paragraph}{4}{\z@}%
     {-1ex \@plus-0.35ex \@minus -0.2ex}%
     {0.5ex \@plus .2ex}%
     {\reset@font\normalsize}}
\renewcommand\subparagraph{\@startsection{subparagraph}{5}{\parindent}%
     {1.5ex \@plus1ex \@minus .2ex}%
     {-1em}%
     {\reset@font\normalsize\bfseries}}


\def\l@section#1#2{\addpenalty{\@secpenalty} \addvspace{1.0em plus 1pt}
 \@tempdima 1.5em \begingroup
 \parindent \z@ \rightskip \@pnumwidth 
 \parfillskip -\@pnumwidth 
 \bfseries \leavevmode #1\hfil \hbox to\@pnumwidth{\hss #2}\par
 \endgroup}
\def\l@subsection{\@dottedtocline{2}{1.5em}{2.3em}}
\def\l@subsubsection{\@dottedtocline{3}{3.8em}{3.2em}}
\def\l@paragraph{\@dottedtocline{4}{7.0em}{4.1em}}
\def\l@subparagraph{\@dottedtocline{5}{10em}{5em}}
\@ifundefined{c@section}{\newcounter{section}}{}
\@ifundefined{c@chapter}{\newcounter{chapter}}{}
\newif\if@mainmatter 
\@mainmattertrue
\def\chaptername{Chapter}
\def\frontmatter{%
  \pagenumbering{roman}
  \def\thechapter{\@roman\c@chapter}
  \def\theHchapter{\roman{chapter}}
  \def\thesection{\@roman\c@section}
  \def\theHsection{\roman{section}}
  \def\@chapapp{}%
}
\def\mainmatter{%
  \cleardoublepage
  \def\thechapter{\@arabic\c@chapter}
  \setcounter{chapter}{0}
  \setcounter{section}{0}
  \pagenumbering{arabic}
  \setcounter{secnumdepth}{6}
  \def\@chapapp{\chaptername}%
  \def\theHchapter{\arabic{chapter}}
  \def\thesection{\@arabic\c@section}
  \def\theHsection{\arabic{section}}
}
\def\backmatter{%
  \cleardoublepage
  \setcounter{chapter}{0}
  \setcounter{section}{0}
  \setcounter{secnumdepth}{2}
  \def\@chapapp{\appendixname}%
  \def\thechapter{\@Alph\c@chapter}
  \def\theHchapter{\Alph{chapter}}
  \appendix
}
\newenvironment{bibitemlist}[1]{%
   \list{\@biblabel{\@arabic\c@enumiv}}%
       {\settowidth\labelwidth{\@biblabel{#1}}%
        \leftmargin\labelwidth
        \advance\leftmargin\labelsep
        \@openbib@code
        \usecounter{enumiv}%
        \let\p@enumiv\@empty
        \renewcommand\theenumiv{\@arabic\c@enumiv}%
	}%
  \sloppy
  \clubpenalty4000
  \@clubpenalty \clubpenalty
  \widowpenalty4000%
  \sfcode`\.\@m}%
  {\def\@noitemerr
    {\@latex@warning{Empty `bibitemlist' environment}}%
    \endlist}

\def\tableofcontents{\section*{\contentsname}\@starttoc{toc}}
\parskip0pt
\parindent1em
\def\Panel#1#2#3#4{\multicolumn{#3}{){\columncolor{#2}}#4}{#1}}
\newenvironment{reflist}{%
  \begin{raggedright}\begin{list}{}
  {%
   \setlength{\topsep}{0pt}%
   \setlength{\rightmargin}{0.25in}%
   \setlength{\itemsep}{0pt}%
   \setlength{\itemindent}{0pt}%
   \setlength{\parskip}{0pt}%
   \setlength{\parsep}{2pt}%
   \def\makelabel##1{\itshape ##1}}%
  }
  {\end{list}\end{raggedright}}
\newenvironment{sansreflist}{%
  \begin{raggedright}\begin{list}{}
  {%
   \setlength{\topsep}{0pt}%
   \setlength{\rightmargin}{0.25in}%
   \setlength{\itemindent}{0pt}%
   \setlength{\parskip}{0pt}%
   \setlength{\itemsep}{0pt}%
   \setlength{\parsep}{2pt}%
   \def\makelabel##1{\upshape ##1}}%
  }
  {\end{list}\end{raggedright}}
\newenvironment{specHead}[2]%
 {\vspace{20pt}\hrule\vspace{10pt}%
  \phantomsection\label{#1}\markright{#2}%

  \pdfbookmark[2]{#2}{#1}%
  \hspace{-0.75in}{\bfseries\fontsize{16pt}{18pt}\selectfont#2}%
  }{}
      \def\TheFullDate{2017-01-15 (revised: 15 January 2017)}
\def\TheID{\makeatother }
\def\TheDate{2017-01-15}
\title{Modelling and Simulation of Microcode based Built-In Self Test Technology for Multiported Memory}
\author{}\makeatletter 
\makeatletter
\newcommand*{\cleartoleftpage}{%
  \clearpage
    \if@twoside
    \ifodd\c@page
      \hbox{}\newpage
      \if@twocolumn
        \hbox{}\newpage
      \fi
    \fi
  \fi
}
\makeatother
\makeatletter
\thispagestyle{empty}
\markright{\@title}\markboth{\@title}{\@author}
\renewcommand\small{\@setfontsize\small{9pt}{11pt}\abovedisplayskip 8.5\p@ plus3\p@ minus4\p@
\belowdisplayskip \abovedisplayskip
\abovedisplayshortskip \z@ plus2\p@
\belowdisplayshortskip 4\p@ plus2\p@ minus2\p@
\def\@listi{\leftmargin\leftmargini
               \topsep 2\p@ plus1\p@ minus1\p@
               \parsep 2\p@ plus\p@ minus\p@
               \itemsep 1pt}
}
\makeatother
\fvset{frame=single,numberblanklines=false,xleftmargin=5mm,xrightmargin=5mm}
\fancyhf{} 
\setlength{\headheight}{14pt}
\fancyhead[LE]{\bfseries\leftmark} 
\fancyhead[RO]{\bfseries\rightmark} 
\fancyfoot[RO]{}
\fancyfoot[CO]{\thepage}
\fancyfoot[LO]{\TheID}
\fancyfoot[LE]{}
\fancyfoot[CE]{\thepage}
\fancyfoot[RE]{\TheID}
\hypersetup{citebordercolor=0.75 0.75 0.75,linkbordercolor=0.75 0.75 0.75,urlbordercolor=0.75 0.75 0.75,bookmarksnumbered=true}
\fancypagestyle{plain}{\fancyhead{}\renewcommand{\headrulewidth}{0pt}}

\date{}
\usepackage{authblk}

\providecommand{\keywords}[1]
{
\footnotesize
  \textbf{\textit{Index terms---}} #1
}

\usepackage{graphicx,xcolor}
\definecolor{GJBlue}{HTML}{273B81}
\definecolor{GJLightBlue}{HTML}{0A9DD9}
\definecolor{GJMediumGrey}{HTML}{6D6E70}
\definecolor{GJLightGrey}{HTML}{929497} 

\renewenvironment{abstract}{%
   \setlength{\parindent}{0pt}\raggedright
   \textcolor{GJMediumGrey}{\rule{\textwidth}{2pt}}
   \vskip16pt
   \textcolor{GJBlue}{\large\bfseries\abstractname\space}
}{%   
   \vskip8pt
   \textcolor{GJMediumGrey}{\rule{\textwidth}{2pt}}
   \vskip16pt
}

\usepackage[absolute,overlay]{textpos}

\makeatother 
      \usepackage{lineno}
      \linenumbers
      
\begin{document}

             \author[1]{Miss. Musle Dipali  B.}

             \author[2]{Miss. Musle Dipali  B.}

             \affil[1]{  Bharati vidyapeeths college of engg for women pune}

\renewcommand\Authands{ and }

\date{\small \em Received: 10 December 2016 Accepted: 1 January 2017 Published: 15 January 2017}

\maketitle


\begin{abstract}
        


Now a day?s embedded memory area and memory density is increasing. Due to this problem of fault is growing exponentionally.It is necessary to detect and repair those faults. There are different methods to detect the faults present in memory. Asynchronous P-MBIST method is used to detect the faults. Simulation result includes asynchronous P-MBIST which detect mismatch of data occurred and it is shown by high fault pulse. To correct the detected fault redundancy circuit is used. This system is implemented using FPGA platform.

\end{abstract}


\keywords{built-in-self test (MBIST), built-in-self repair (BISR), asynchronous P-MBIST, microcode MBIST multiported memory, redundancy logic array, field progr}

\begin{textblock*}{18cm}(1cm,1cm) % {block width} (coords) 
\textcolor{GJBlue}{\LARGE Global Journals \LaTeX\ JournalKaleidoscope\texttrademark}
\end{textblock*}

\begin{textblock*}{18cm}(1.4cm,1.5cm) % {block width} (coords) 
\textcolor{GJBlue}{\footnotesize \\ Artificial Intelligence formulated this projection for compatibility purposes from the original article published at Global Journals. However, this technology is currently in beta. \emph{Therefore, kindly ignore odd layouts, missed formulae, text, tables, or figures.}}
\end{textblock*}


\let\tabcellsep& 	 	 		 
\section[{I. Introduction}]{I. Introduction}\par
ccording to the ITRS 2015,Now a days the memory area is increasing than logic area in SOCs.Fig.  {\ref 1} \hyperref[b0]{[1]} shows that shrinking the technologies give rise to defect and new fault models.Thus, the new trends in Multiported memory testing will be driven by the following items. BIST: The new fault and new defects eliminate using BIST. The only solution that allows at-speed testing for embedded memories, it has generate fault detection and coverage, the higher repair efficiency only detecting the faults is no longer sufficient for SOCs so memory repair is also necessary for this purpose both diagnosis and repair algorithm are required. BISR: Combining BIST with efficient and low cost repair schemes in order to improve the yield and system reliability as well.\par
Fig.  {\ref 1} : Embedded Memories in Future SOCs \hyperref[b0]{[1]} Auhtor ? ?: Department of Electronics and telecommunication Bharati Vidyapeeth's College of Engineering for Women Pune, 43 Savitribai Phule Pune University. e-mails: srpatil44@gmail.com, dipali.musleb@gmail.com There are two methods which are efficiently used. These methods are as follow:  
\section[{II. Related Work}]{II. Related Work}\par
Dr. R.K. Sharma et al. \hyperref[b1]{[2]} introduced Redundancy Array Logic and BISR mechanism used to low cost repair the fault and to improve the system reliability.\par
Bo-Cheng Charles Lai et al. \hyperref[b3]{[4]} introduced designs of multiported memories that leverage BRAMs have been proposed to attain better utilization of FPGA resources as well as system performance. BRAMs in an FPGA can support two access ports that can be used as either a read or a write port. 
\section[{A}]{A}\par
Global Journal of Researches in Engineering ( ) Volume XVII Issue II Version I Yash Jyothi et al. \hyperref[b0]{[1]} introduced Asynchronous P-MBIST method for fault detection and repair of multiported memory. The main advantage is to get power efficient P-MBIST, it is being proposed to use handshaking signals instead of using clock and implemented on FPGA. Clocks are used to synchronize the test blocks on chip and handshaking signals are used to communicate between blocks of test controller. 
\section[{III. built-in self test (bist)}]{III. built-in self test (bist)}\par
Memory Built-In Self Test is test circuitry used to test on-chip memory devices. It contains finite state machine to generate test vectors to test vectors to test memory during test mode. Test coller includes Address, Data, read/write control. This address, data and read/write control signal is given as input to comparator and multiplexer. Multiplexer uses two modes of operations: Normal mode-In normal mode memory acts as a normal memory. Test Mode-During test mode test coller provides data and address to memory for testing purpose. In test mode while performing read operation data from test coller and output of memory are given to comparator for fault detection. Then, comparator compares test vectors with memory output. If, memory is working properly then, No Fault is detected and it is declared as memory is fault free but, if fault pulse becomes high it shows that memory under test is faulty.  
\section[{Implementation of Asynchronous p-mbist}]{Implementation of Asynchronous p-mbist}\par
The block diagram shown in Fig. \hyperref[fig_2]{3}     {\ref I}. \hyperref[b0]{[1]} Table No.1: Microcode Instruction \hyperref[b0]{[1]} V. 
\section[{Flowchart of Asynchronous p-mbist}]{Flowchart of Asynchronous p-mbist}\par
The flow of asynchronous P-MBIST is as shown in fig .  {\ref 4}, fig.  {\ref 5}     
\section[{Asynchronous p-mbist Simulation}]{Asynchronous p-mbist Simulation}\par
The simulation of asynchronous P-MBIST is depending upon request signal and mode. Output Response: Normal Mode: When mode=0, MUX selects normal mode, then test controller is off so as comparator is off. At this moment memory acts as normal memory without under test and generates external address and data if rw=0(i.e. reads address and corresponding data).During this mode as comparator is off, no fault pulse is generated. In this mode, memoutdata (memory output) data is data (External data) provided for normal memory operation. Test Mode: If mode=1, Memory is under test. If req=1, microcode instruction storage generates Read/Write control for test collar. Test collar writes data if tcrw=0 otherwise read to memory through MUX. The data from test collar and output of memory is compared in comparator. If mismatch happens at output of comparator, comparator generates fault pulse=1 otherwise fault pulse=0 \hyperref[b0]{[1]}.  During the normal mode each incoming address is compared with the address field of programmed redundant words. If there is a match, the data field of the redundant word is used along with the faulty memory location for reading and writing data. The output multiplexer of Redundant Array Logic then ensures that in case of a match, the redundant word data field is selected over the data read out ( = 0) of the faulty location in case of a read signal. This can be easily understood by the redundancy word detail shown in Figure \hyperref[fig_6]{7}. VII. Results 
\section[{VI.}]{VI.} 
\section[{Repair Module}]{Repair Module} 
\section[{Single port Memory}]{Single port Memory}\par
The single port memory support single read and write operation.  \begin{figure}[htbp]
\noindent\textbf{2}\includegraphics[]{image-2.png}
\caption{\label{fig_0}Fig. 2 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-3.png}
\caption{\label{fig_1}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{3}\includegraphics[]{image-4.png}
\caption{\label{fig_2}Fig. 3 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-5.png}
\caption{\label{fig_3}Address}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{456}\includegraphics[]{image-6.png}
\caption{\label{fig_4}Fig. 4 :Fig. 5 :Fig. 6 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{8}\includegraphics[]{image-7.png}
\caption{\label{fig_5}Fig. 8 .}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{7}\includegraphics[]{image-8.png}
\caption{\label{fig_6}Fig. 7 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{88}\includegraphics[]{image-9.png}
\caption{\label{fig_7}Fig. 8 :Fig. 8 .}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{9}\includegraphics[]{image-10.png}
\caption{\label{fig_8}Fig. 9 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{10312}\includegraphics[]{image-11.png}
\caption{\label{fig_9}Fig. 10 :F 3 .Fig. 12 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{} \par 
\begin{longtable}{P{0.4038674033149171\textwidth}P{0.15966850828729282\textwidth}P{0.2395027624309392\textwidth}P{0.04696132596685083\textwidth}}
Year 2017\tabcellsep \tabcellsep \\
22\tabcellsep \tabcellsep \\
II Version I\tabcellsep \tabcellsep Data\tabcellsep R/W signal\\
( ) Volume XVII Issue\tabcellsep MBIST Controller\tabcellsep Input MUX Multiported\\
Journal of Researches in Engineering\tabcellsep Redundancy circuit\tabcellsep Memory Output MUX Data Out\\
Global\tabcellsep \tabcellsep \end{longtable} \par
  {\small\itshape [Note: F i. If there is request from Microcode Instruction Storage (MIS) to Pulse generator (PG), then PG sends Start Pulse to MIS to start the asynchronous operation. In next step MIS checks for request from Test Collar (TC), if so it sends microcode instructions to TC. TC then sends the acknowledgement signal to pulse generator indicates that TC is getting instructions from MIs. ii. Output of TC Data which includes test address, corresponding data and R/W control signals send to input multiplexer (MUX) if MUX sends high pulse of request. Multiplexer is originally not a multiplexer but concept used for this block is according to working of normal multiplexer. Here mode signal is select line for MUX. iii. If mode=1then PMBIST works in test mode then it selects TC data. If mode=0 then it is in normal mode, during this mode test circuitry is in ideal condition and memory works as normal memory without under test and sends output of external Address, corresponding data and R/W control signal. When MUX is under test mode then it sends TC data to memory if request signal is high from memory to MUX.]} 
\caption{\label{tab_1}}\end{figure}
 			\footnote{Year 2017 F © 2017 Global Journals Inc. (US)} 			\footnote{Modelling and Simulation of Microcode based Built-In Self Test Technology for Multiported Memory © 2017 Global Journals Inc. (US)} 			\footnote{Year 2017 F © 2017 Global Journals Inc. (US) Fig. 11:} 			\footnote{Year 2017 F} 		 		\backmatter  			 
\subsection[{Global}]{Global}			 			  				\begin{bibitemlist}{1}
\bibitem[Hassenmestiri et al. ()]{b0}\label{b0} 	 		‘A high speed AES design resistant to fault injection attacks’.  		 			Fatmakahri Hassenmestiri 		,  		 			Mohsen Belgacembouallegue 		,  		 			Machhout 		.  	 	 		\textit{Microprocessors and Microsystems journal}  		2016. Elsevier. p. .  	 
\bibitem[Bernardi et al. ()]{b8}\label{b8} 	 		‘A programmable BIST for DRAM testing and diagnosis’.  		 			P Bernardi 		,  		 			M Grosso 		,  		 			M S Reorda 		,  		 			Y Zhang 		.  	 	 		\textit{Test Conference (ITC)},  				2010. 2010. p. .  	 
\bibitem[Malazgirt et al. (2014)]{b4}\label{b4} 	 		‘Application specific multi-port memorycustomization in FPGAs’.  		 			G A Malazgirt 		,  		 			H E Yantir 		,  		 			A Yurdakul 		,  		 			S Niar 		.  	 	 		\textit{Proc. IEEE Int.Conf. Field Program. Logic Appl. (FPL)},  				 (IEEE Int.Conf. Field Program. Logic Appl. (FPL))  		Sep. 2014. p. .  	 
\bibitem[Lai et al. ()]{b3}\label{b3} 	 		‘Efficient Designs of Multiported Memory on FPGA’.  		 			Bo-Cheng Charles Lai 		,  		 			Ieee Member 		,  		 			Jiun-Liang Lin 		.  	 	 		\textit{ieee transactions on very large scale integration (vlsi) systems},  				2016.  	 
\bibitem[Laforest and Steffan]{b9}\label{b9} 	 		\textit{Efficient multiported memories for FPGAs},  		 			C E Laforest 		,  		 			J G Steffan 		.  		 	 	 (inProc. 18th Annu) 
\bibitem[Int ()]{b10}\label{b10} 	 		 			Acm/Sigda Int 		.  		\textit{Symp. Field Program.Gate Arrays},  				2010. p. .  	 
\bibitem[Hamdioui ()]{b5}\label{b5} 	 		‘Memory Test Optimizationfor Parasitic Bit LineCoupling in SRAMs’.  	 	 		\textit{IEEE International Test Conference},  				 			Sandra Irobi Zaid Al-Ars Said Hamdioui 		 (ed.)  		2010.  	 
\bibitem[Dr et al. ()]{b1}\label{b1} 	 		‘Modeling and Simulation of Multi-Operation Microcode based Built-In Self Test for Memory Fault Detection and Repair’.  		 			R K Dr 		,  		 			Sharma Aditi 		,  		 			Sood 		.  	 	 		\textit{IEEE Annual Symposium on VLSI}  		2010.  	 
\bibitem[Haron et al. ()]{b6}\label{b6} 	 		‘Modelling and Simulation of Microcode Built-In Self test Architecture for Embedded Memories’.  		 			N Z Haron 		,  		 			S A M Junos 		,  		 			A S A Aziz 		.  	 	 		\textit{Proc. of IEEE International Symposium on Communications and Information Technologies},  				 (of IEEE International Symposium on Communications and Information Technologies)  		2007. p. .  	 
\bibitem[Laforest et al. ()]{b12}\label{b12} 	 		‘Multi-ported memories for FPGAs via XOR’.  		 			C E Laforest 		,  		 			M G Liu 		,  		 			E Rapati 		,  		 			J G Steffan 		.  	 	 		\textit{Proc. 20th Annu. ACM/SIGDA Int. Symp. Field Program. Gate Arrays (FPGA)},  				 (20th Annu. ACM/SIGDA Int. Symp. Field Program. Gate Arrays (FPGA))  		2012. p. .  	 
\bibitem[Prof et al. ()]{b2}\label{b2} 	 		‘Optimization of Microcode Built-In Self Test By Enhanced Faults Coverage for Embedded Memory’.  		 			Vinod Prof 		,  		 			Mohammed Kapse 		,  		 			Arif 		.  	 	 		\textit{IEEE Students' Conference on Electrical, Electronics and Computer Science},  				2012.  	 
\bibitem[Xilinx (2016)]{b11}\label{b11} 	 		\textit{Series FPGAs Configurable Logic Block User Guide,accessed on},  		 			Xilinx 		.  		 \url{http://www.xilinx.com/support/documentation/user\textunderscore guides/ug474\textunderscore 7Series\textunderscore CLB.pdf}  		May 30, 2016.  	 
\bibitem[Hamdioui et al. ()]{b7}\label{b7} 	 		‘State-of-art and Future Trends in Testing Embedded Memories’.  		 			S Hamdioui 		,  		 			G N Gaydadjiev 		,  		 			A J Van De Goor 		.  	 	 		\textit{International Workshop on Memory Technology, Design and Testing (MTDT'04)},  				2004.  	 
\end{bibitemlist}
 			 		 	 
\end{document}
