# I. Introduction

ccording to the ITRS 2015,Now a days the memory area is increasing than logic area in SOCs.Fig. 1 [1] shows that shrinking the technologies give rise to defect and new fault models.Thus, the new trends in Multiported memory testing will be driven by the following items. BIST: The new fault and new defects eliminate using BIST. The only solution that allows at-speed testing for embedded memories, it has generate fault detection and coverage, the higher repair efficiency only detecting the faults is no longer sufficient for SOCs so memory repair is also necessary for this purpose both diagnosis and repair algorithm are required. BISR: Combining BIST with efficient and low cost repair schemes in order to improve the yield and system reliability as well.

Fig. 1 : Embedded Memories in Future SOCs [1] Auhtor ? ?: Department of Electronics and telecommunication Bharati Vidyapeeth's College of Engineering for Women Pune, 43 Savitribai Phule Pune University. e-mails: srpatil44@gmail.com, dipali.musleb@gmail.com There are two methods which are efficiently used. These methods are as follow: 


# II. Related Work

Dr. R.K. Sharma et al. [2] introduced Redundancy Array Logic and BISR mechanism used to low cost repair the fault and to improve the system reliability.

Bo-Cheng Charles Lai et al. [4] introduced designs of multiported memories that leverage BRAMs have been proposed to attain better utilization of FPGA resources as well as system performance. BRAMs in an FPGA can support two access ports that can be used as either a read or a write port.


# A

Global Journal of Researches in Engineering ( ) Volume XVII Issue II Version I Yash Jyothi et al. [1] introduced Asynchronous P-MBIST method for fault detection and repair of multiported memory. The main advantage is to get power efficient P-MBIST, it is being proposed to use handshaking signals instead of using clock and implemented on FPGA. Clocks are used to synchronize the test blocks on chip and handshaking signals are used to communicate between blocks of test controller.


# III. built-in self test (bist)

Memory Built-In Self Test is test circuitry used to test on-chip memory devices. It contains finite state machine to generate test vectors to test vectors to test memory during test mode. Test coller includes Address, Data, read/write control. This address, data and read/write control signal is given as input to comparator and multiplexer. Multiplexer uses two modes of operations: Normal mode-In normal mode memory acts as a normal memory. Test Mode-During test mode test coller provides data and address to memory for testing purpose. In test mode while performing read operation data from test coller and output of memory are given to comparator for fault detection. Then, comparator compares test vectors with memory output. If, memory is working properly then, No Fault is detected and it is declared as memory is fault free but, if fault pulse becomes high it shows that memory under test is faulty. 


# Implementation of Asynchronous p-mbist

The block diagram shown in Fig. 3    I. [1] Table No.1: Microcode Instruction [1] V.


# Flowchart of Asynchronous p-mbist

The flow of asynchronous P-MBIST is as shown in fig . 4, fig. 5    


# Asynchronous p-mbist Simulation

The simulation of asynchronous P-MBIST is depending upon request signal and mode. Output Response: Normal Mode: When mode=0, MUX selects normal mode, then test controller is off so as comparator is off. At this moment memory acts as normal memory without under test and generates external address and data if rw=0(i.e. reads address and corresponding data).During this mode as comparator is off, no fault pulse is generated. In this mode, memoutdata (memory output) data is data (External data) provided for normal memory operation. Test Mode: If mode=1, Memory is under test. If req=1, microcode instruction storage generates Read/Write control for test collar. Test collar writes data if tcrw=0 otherwise read to memory through MUX. The data from test collar and output of memory is compared in comparator. If mismatch happens at output of comparator, comparator generates fault pulse=1 otherwise fault pulse=0 [1].  During the normal mode each incoming address is compared with the address field of programmed redundant words. If there is a match, the data field of the redundant word is used along with the faulty memory location for reading and writing data. The output multiplexer of Redundant Array Logic then ensures that in case of a match, the redundant word data field is selected over the data read out ( = 0) of the faulty location in case of a read signal. This can be easily understood by the redundancy word detail shown in Figure 7. VII. Results


# VI.


# Repair Module


# Single port Memory

The single port memory support single read and write operation.  
2![Fig. 2: Structure of P-MBIST](image-2.png "Fig. 2 :")
![[1] the asynchronous P-MBIST contains handshaking signals instead of using clock. Request and acknowledge signals perform communication in Asynchronous P-MBIST.](image-3.png "")
3![Fig. 3: Block Diagram of Asynchronous P-MBIST [1] The control circuitry contain following blocks: Microcode Instruction storage unit, Test collar, comparator, Clock Generator. The Test Collar circuitry consists of Address Generator, RW Control and Data Control. Common Clock is used for Synchronous MBIST. In Microcode Instruction Storage (MIS), 4 instruction operations are stored that are R0, R1, W0, W1 as shown in TableI.[1] ](image-4.png "Fig. 3 :")
![](image-5.png "Address")
456![Fig. 4: Flowchart Step-I](image-6.png "Fig. 4 :Fig. 5 :Fig. 6 :")
8![Fig.8.Shows the Repair Module including the redundancy array and output multiplexer and its interfacing with the existing BIST module. Fig.7 An array of redundant words placed in parallel with the memory. The following interface signals are taken from the MBIST logic:1) A fault pulse indicating a faulty location address,2) Fault address,3)](image-7.png "Fig. 8 .")
7![Fig. 7: Redundancy Word Line [2] b) Mode 2: Normal ModeDuring the normal mode each incoming address is compared with the address field of programmed redundant words. If there is a match, the data field of the redundant word is used along with the faulty memory location for reading and writing data. The output multiplexer of Redundant Array Logic then ensures that in case of a match, the redundant word data field is selected over the data read out ( = 0) of the faulty location in case of a read signal. This can be easily understood by the redundancy word detail shown in Figure7.](image-8.png "Fig. 7 :")
88![Fig. 8: Redundancy Array Logic [2] Fig.8.Shows the simulated waveform of fault diagnosis module, magnified at seventh pulse to indicate how signals like 'fault pulse ', 'faulty location addresses and 'correct data' are generated by this module for successful interfacing with the Redundancy Array logic.[2]](image-9.png "Fig. 8 :Fig. 8 .")
9![Fig.9: Result of Single port Memory2. Dual port MemoryThe single port memory support dual read and write operation.](image-10.png "Fig. 9 :")
10312![Fig.10: Result of Dual port Memory](image-11.png "Fig. 10 :F 3 .Fig. 12 :")
Year 201722II Version IDataR/W signal( ) Volume XVII IssueMBIST ControllerInput MUX MultiportedJournal of Researches in EngineeringRedundancy circuitMemory Output MUX Data OutGlobalF i. If there is request from Microcode Instruction Storage (MIS) to Pulse generator (PG), then PG sends Start Pulse to MIS to start the asynchronous operation. In next step MIS checks for request from Test Collar (TC), if so it sends microcode instructions to TC. TC then sends the acknowledgement signal to pulse generator indicates that TC is getting instructions from MIs. ii. Output of TC Data which includes test address, corresponding data and R/W control signals send to input multiplexer (MUX) if MUX sends high pulse of request. Multiplexer is originally not a multiplexer but concept used for this block is according to working of normal multiplexer. Here mode signal is select line for MUX. iii. If mode=1then PMBIST works in test mode then it selects TC data. If mode=0 then it is in normal mode, during this mode test circuitry is in ideal condition and memory works as normal memory without under test and sends output of external Address, corresponding data and R/W control signal. When MUX is under test mode then it sends TC data to memory if request signal is high from memory to MUX.
			Year 2017 F © 2017 Global Journals Inc. (US)
			Modelling and Simulation of Microcode based Built-In Self Test Technology for Multiported Memory © 2017 Global Journals Inc. (US)
			Year 2017 F © 2017 Global Journals Inc. (US) Fig. 11:
			Year 2017 F
		
		
			

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