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\title{FPGA Based Hybrid Digital PWM for DC-DC Voltage Regulator}
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             \author[1]{Joseph Anthony  Prathap}

             \author[2]{Joseph Anthony  Prathap}

             \affil[1]{  }

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\date{\small \em Received: 14 December 2016 Accepted: 5 January 2017 Published: 15 January 2017}

\maketitle


\begin{abstract}
        


This In general, telecommunication applications require low voltage, high current and reduced size power supplies. Selection of high switching frequency helps in the reduction of the DC-DC converter size. In this work, Digital PI (DPI) enables the Digital Pulse Width Modulation (DPWM) generator for generating high switching frequencies are developed and implemented using VHDL coding and Xilinx Spartan 3A DSP Field Programmable Gate Array (FPGA) kit. Hardware result of voltage regulation depicts the superiority and robustness of the proposed DPI enabled DPWM (MD-DPWM) methods under line and load disturbances. The MD-DPWM technique can be used to generate a very high switching frequency up to 1 MHz and more. Also the MD-DPWM proves to be cost effective, as it consumes low power and area.

\end{abstract}


\keywords{digital pulse width modulation, digital proportional integral-dc-to-dc buck converter, xilinx spartan 3A DSP field programmable gate array.}

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\let\tabcellsep& 	 	 		 
\section[{I. Introduction}]{I. Introduction}\par
uck converter is a circuit which step downs the voltage and step ups the current. A basic buck converter circuits requires inductor, diode and transistor as switch. As per the control of the switch by the PWM signals the inductor acts against the input voltage. The DPWM design involves digital circuits like adders, flip-flops, multiplexers, counters and shift registers.\par
DPWM has advantages like easy design, high accuracy, low area and low power consumption. High resolution digitally controlled DC-DC buck converter is designed without the use of high frequency clock \hyperref[b0]{[1]}. FPGA based implementation of the DPWM is very simple comparatively consuming of few memories, multipliers and adders \hyperref[b1]{[2]}. DPWM architecture developed with FPGA implies high reliability, linearity and low latency \hyperref[b2]{[3]}. A brushless DC machines can be digitally controlled by FPGA implementation with no additional hardware and hence has low design complexity \hyperref[b3]{[4]}.\par
A DPWM technique in \hyperref[b4]{[5]} gives consistent offtime and on-time control under heavy load and light load conditions with reduced switching losses. FPGA based high resolution DPWM designed using a digital clock manager and I/O delay elements have low cost and higher clock frequency \hyperref[b5]{[6]}. In this work, the performances of the DC-DC buck converter with the DPWM as voltage regulator is analyzed. 
\section[{II. Dc -Dc Buck Converter}]{II. Dc -Dc Buck Converter}\par
The closed loop DC-DC buck converter with the proposed DPI enables the DPWM technique is shown in the Fig. \hyperref[fig_0]{1}. 
\section[{DC-DC Buck Converter}]{DC-DC Buck Converter} 
\section[{Analog to Digital}]{Analog to Digital}\par
Converter AD7266 The output voltage of the buck converter is less than the input voltage and is controlled by the duty cycle "d". The duty cycle "d" is the ratio of the ON period to the total period cycle of the controlling square pulse. 
\section[{Modified}]{Modified} 
\section[{d = T on T}]{d = T on T}\par
Where "Ton"refers to the ON period. "T" refers to the total time period of the cycle. The operation of the buck converter is related to the duty cycle as given belowV out = d. V in\par
Where "d" is the duty cycle. "Vin" is the input voltage of the buck converter. "Vout" is output voltage of the buck converter.\par
The digital switching control has more advantages like easy designing, high manipulation power, upgradable, immune to environmental changes, easy debugging.\par
In our work, the FPGA based DPWM DC-DC buck voltage regulator, is implemented which satisfies the demand of low voltage and high current application. ADC is utilized for the purpose of acquiring the feedback values of the DC-DC buck converter into the FPGA. ADC IC AD7266 has Successive Approximation Circuit (SAC) and is used for real time implementation. The FPGA based ADC architecture helps in the evaluation of digital error with high accuracy \hyperref[b6]{[7]}. The Digital PI (DPI) control algorithm is designed using VHDL coding enables the DPWM. The Modified DPI enabled DPWM (MD-DPWM) generators are implemented by FPGA and found to perform efficiently for the disturbances and component variation. The AD7266 is provided to access the analog value in the form of digital equivalence (2N). 
\section[{III. Digital Pulse Width Modulation Methods}]{III. Digital Pulse Width Modulation Methods}\par
The Digital Pulse Width Modulated (DPWM) signal is generated using logical design. The DPWM is generated by three methods. They are i) Counter DPWM method. (CDPWM) ii) Delay line DPWM method. (DDPWM) iii) Hybrid DPWM method. (HDPWM) Using ModelSim, the three DPWM methods are simulated. From the simulated results, the HDPWM generator is found to be advantages when compared to the CDPWM and DDPWM. The CDPWM require high frequency system clock and thus has high power consumption. The DDPWM occupies more area increasing the cost. The relationship of the clock frequency and the switching frequency for the DPWM generator is  Resolution refers to the number of bits used in the design. In this work, the three MD-DPWM generators are designed using 2 11 bit resolution. The MD-CDPWM generator uses a 2 11 bit (2047 count) counter. The MD-DDPWM generator uses the 2048:1 multiplexer. The MD-HDPWM generator uses 2 11 bit resolution in which 2 5 bit is used for the MD-DDPWM generation part and 2 6  bit is used for the MD-CDPWM generation part. The frequency of the DPWM generator is 12.5 KHz in the hardware due to the limitations in frequency range with the laboratory prototype. To achieve this frequency, the VHDL coding utilizes the scaled value given by the formula.F CLK = F SW x 2 n F SW - 
\section[{Scaled\textunderscore value}]{Scaled\textunderscore value}= 1 2 n X Output frequency X Clock period\par
Where Clock period is 100 ns Output frequency is 12.5 KHz 
\section[{V. HARDWARE DETAILS}]{V. HARDWARE DETAILS}\par
The Xilinx Spartan 3A DSP FPGA is used for the design of the DC-DC buck type voltage regulator using MD-HDPWM. The Xilinx Spartan 3A DSP has IC AD7266 for the design of ADC. The set point variations are provided by the two variable push switches. The 16*4 LCD display is activated by the VHDL code. The VHDL codes for the DPI and ADC are designed with 10 times of the actual values to accomplish the FPGA requirements. This scaling is done to make sure that the fractional changes of the ADC and DPI are considered in the design, as the Xilinx Spartan 3A DSP kit do not support the float value implementation.\par
The AD7266 is 8 channels SAR ADC with IC which operates from 2.7V to 5.25V of supply. The ADC performs two functions of sampling and conversion of two channels simultaneously. These conversion values are concurrently accessible in separate data lines. When operated at 3V, the AD7266 gives a throughput rate of 1.5 MSPS with maximum power dissipation of 11.4 mW. Thus low power consumption for high throughput is achieved. The AD7266 has zero pipeline delay; since the sampling control of the two SAR ADCs are accurate. The ADC has two input ranges like 0V to VREF and 2*VREF 
\section[{VI. RESULTS AND DISCUSSIONS}]{VI. RESULTS AND DISCUSSIONS}\par
the set-point change and Fig. \hyperref[fig_0]{13} shows experimental DSO output for the positive and negative line disturbances. Fig. \hyperref[fig_4]{14\&15} indicate the performance of the MD-HDPWM based DC-DC buck converter in closed loop with load disturbances from 445? to 595? and 595? to 445? respectively. The set point is 10 V and input voltage is 20V. The settling time measured during the negative load disturbance with MD-HDPWM seems to be very minimal. Fig. \hyperref[fig_0]{16\&17} show the experimental DSO response of load disturbance from 445 ? to 595? and from 595? to 445? respectively for the MD-HDPWM in closed loop. Fig. \hyperref[fig_0]{18} shows experimental output response when the load is changed from 470 ? to 495? and from 495? to 470? using MD-DDPWM. Fig. \hyperref[fig_0]{19} shows experimental output for the negative load disturbance from 445? to 295? using MD-DDPWM. The RTL schematic for the MD-HDPWM technique is presented in Fig.  {\ref 20}. Fig. \hyperref[fig_0]{21},22,\&23 show the design utilization chart for the MD-CDPWM, MD-DDPWM and MD-HDPWM respectively. The experimental setup of DC-DC buck converter using the Xilinx Spartan 3A DSP is shown in Fig. \hyperref[fig_4]{24}. 
\section[{VII. COMPARISON AND ANALYSIS}]{VII. COMPARISON AND ANALYSIS}\par
Table  {\ref I} shows that the Modified DPI enabled HDPWM has lower steady state error and low settling time for the step change variation. The peak overshoot percentage is also less in MD-HDPWM. Table  {\ref I}    
\section[{b) Experimental Results}]{b) Experimental Results}\par
The simulation outputs of the MD-DPWM generator using the above mentioned three techniques are given below in Fig. \hyperref[fig_4]{4},5,\&6 using ModelSim. The open loop response under line disturbance for the DC-DC buck converter is given for the three MD-DPWM techniques in Fig.  {\ref 7(a),(b)\&(c}). Fig.  {\ref 8(a),(b)\&(c}) depict the open loop response under load disturbance for the DC-DC buck converter for the three MD-DPWM techniques. Fig.  {\ref 9} show the start-up transient response along with the set-point variation of closed loop DC-DC buck converter using MD-HDPWM. The CSV file format is plotted using excel sheet format. The time transient parameters like settling time (t s ), rise time (t r ), delay time (t d ), peak time (t p ) and overshoot percentage (\%MP) are also calculated and displayed in the graph. The input voltage is 20V.The set point variation is from 11V to 12.8 V for MD-HDPWM.\par
Fig. \hyperref[fig_0]{10} shows the analysis for the closed loop response under increased line disturbance from 10.4V to 12V and Fig. \hyperref[fig_0]{11} shows the analysis for the closed loop response under decreased line disturbances from 10.4V to 8.8V for the MD-HDPWM technique. The line voltage in this work are suddenly increased from 18V to 20V and decreased from 20V to 18V. Timing performance indices of the hybrid method are found to have less settling time comparatively and hence hybrid is selected. Fig. \hyperref[fig_0]{12} shows experimental DSO response for      
\section[{VIII. CONCLUSION}]{VIII. CONCLUSION}\par
Simulation results show the possibilities of achieving high switching frequency up to 16MHz DPWM. Hardware results show the feasibility of the proposed technique for the available prototype model in our laboratory and found to be satisfactory. The Modified DPI enabled DPWM generators also perform voltage regulation of the power supply. The FPGA based Modified DPI enabled Hybrid based DPWM voltage regulator is found to be immune to circuit component variations, and also to line-load disturbances.\begin{figure}[htbp]
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\noindent\textbf{1} \par 
\begin{longtable}{P{0.3874149659863946\textwidth}P{0.15034013605442176\textwidth}P{0.15034013605442176\textwidth}P{0.16190476190476188\textwidth}}
Method\tabcellsep MD-CDPWM\tabcellsep MD-DDPW M\tabcellsep MD-HDPWM\\
Settling Time (ts)\tabcellsep 4.71\tabcellsep 6.2\tabcellsep 5.1\\
Rise Time (tr)\tabcellsep 0.035\tabcellsep 0.002\tabcellsep 0.0419\\
Delay Time (td)\tabcellsep 0.032\tabcellsep 0.023\tabcellsep 0.0385\\
Peak Time (tp)\tabcellsep 0.04\tabcellsep 0.03\tabcellsep 0.164\end{longtable} \par
  {\small\itshape [Note: Table for MD-CDPWM in Xilinx Spartan 3A FPGA Fig. 22: Design Utilization Table for MD-DDPWM in Xilinx Spartan 3A FPGAFig. 23: Design Utilization Table for MD-HDPWM in Xilinx Spartan 3A FPGA Fig. 24: Experimental setup for the Modified DPI enabled DPWM based DC-DC buck converter using FPGA]} 
\caption{\label{tab_0}Table 1 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{2} \par 
\begin{longtable}{P{0.48169596690796274\textwidth}P{0.051861427094105475\textwidth}P{0.1046018614270941\textwidth}P{0.034281282316442604\textwidth}P{0.07911065149948293\textwidth}P{0.0984488107549121\textwidth}}
\multicolumn{5}{l}{Increased Line Disturbance}\\
Methods\tabcellsep \multicolumn{2}{l}{MD-CDPWM}\tabcellsep \multicolumn{2}{l}{MD-DDPWM}\tabcellsep MD-HDPWM\\
\multicolumn{2}{l}{Rise Time in s (tr)}\tabcellsep 0.2\tabcellsep \multicolumn{2}{l}{0.3}\tabcellsep 0.2\\
\multicolumn{2}{l}{Time Delay in s (tp)}\tabcellsep 0.1\tabcellsep \multicolumn{2}{l}{0.1}\tabcellsep 0.1\\
\multicolumn{2}{l}{Settling Time in s (ts)}\tabcellsep 3.8\tabcellsep \multicolumn{2}{l}{2.7}\tabcellsep 1.6\\
\multicolumn{3}{l}{Percentage Overshoot(\%MP) 14.286\%}\tabcellsep \multicolumn{2}{l}{17.647\%}\tabcellsep 15.38\%\\
\multicolumn{2}{l}{Output Voltage Ripple}\tabcellsep 0.04\tabcellsep \multicolumn{2}{l}{0.04}\tabcellsep 0.03846\\
\multicolumn{2}{l}{Initial Value before disturbance}\tabcellsep 9.8 V\tabcellsep \multicolumn{2}{l}{10.2 V}\tabcellsep 10.4 V\\
\multicolumn{2}{l}{Peak Value at disturbance}\tabcellsep 11.2 V\tabcellsep \multicolumn{2}{l}{12 V}\tabcellsep 12 V\\
Methods\tabcellsep \tabcellsep \multicolumn{2}{l}{MD-CDPWM}\tabcellsep MD-DDPWM\tabcellsep MD-HDPWM\\
\multicolumn{2}{l}{Rise Time in s (tr)}\tabcellsep 0.2\tabcellsep \tabcellsep 0.2\tabcellsep 0.23\\
\multicolumn{2}{l}{Time Delay in s (tp)}\tabcellsep 0.142\tabcellsep \tabcellsep 0.135\tabcellsep 0.13\\
\multicolumn{2}{l}{Settling Time in s (ts)}\tabcellsep 3.26\tabcellsep \tabcellsep 2.82\tabcellsep 2.62\\
\multicolumn{2}{l}{Percentage Overshoot (\% MP)}\tabcellsep \multicolumn{2}{l}{14.2857\%}\tabcellsep 13.725\%\tabcellsep 15.38\%\\
\multicolumn{2}{l}{Output Voltage Ripple}\tabcellsep 0.04\tabcellsep \tabcellsep 0.04\tabcellsep 0.04\\
\multicolumn{2}{l}{Initial Value before disturbance}\tabcellsep 9.8 V\tabcellsep \tabcellsep 10.2 V\tabcellsep 10.4 V\\
\multicolumn{2}{l}{Minimum Value at disturbance}\tabcellsep 8.4 V\tabcellsep \tabcellsep 8.8V\tabcellsep 8.8 V\\
Methods\tabcellsep MD-CDPWM\tabcellsep \multicolumn{2}{l}{MD-DDPWM}\tabcellsep MD-HDPWM\\
\tabcellsep \tabcellsep \tabcellsep \tabcellsep 2 11 =2 6 +2 5\\
Resolution with specification\tabcellsep 2 11 -bit Counter Designed\tabcellsep \multicolumn{3}{l}{2 11 2048 : 1 Mux Designed}\tabcellsep (2 6 -bit Counter \& 32:1 Mux\\
\tabcellsep \tabcellsep \tabcellsep \tabcellsep Designed)\\
Number of Sliced Flip Flops\tabcellsep 665\tabcellsep \multicolumn{2}{l}{2716}\tabcellsep 697\\
Number of 4 input LUTs\tabcellsep 1633\tabcellsep \multicolumn{2}{l}{2670}\tabcellsep 1657\\
Number of occupied slices\tabcellsep 1090\tabcellsep \multicolumn{2}{l}{3659}\tabcellsep 1130\\
Number of bonded IOBs\tabcellsep 37\tabcellsep \multicolumn{2}{l}{41}\tabcellsep 37\\
Average Fan-out\tabcellsep \tabcellsep \tabcellsep \\
of Non-clock\tabcellsep 2.96\tabcellsep \multicolumn{2}{l}{2.59}\tabcellsep 2.95\\
nets\tabcellsep \tabcellsep \tabcellsep \end{longtable} \par
 
\caption{\label{tab_1}Table 2 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{3} \par 
\begin{longtable}{}
\end{longtable} \par
 
\caption{\label{tab_2}Table 3 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{4} \par 
\begin{longtable}{}
\end{longtable} \par
  {\small\itshape [Note: F © 2017 Global Journals Inc. (US)]} 
\caption{\label{tab_3}Table 4 :}\end{figure}
 			\footnote{Year 2017 F © 2017 Global Journals Inc. (US)} 			\footnote{© Global Journals Inc. (US)} 			\footnote{© 2017 Global Journals Inc. (US)} 		 		\backmatter  			  				\begin{bibitemlist}{1}
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\end{document}
