# I. Introduction uck converter is a circuit which step downs the voltage and step ups the current. A basic buck converter circuits requires inductor, diode and transistor as switch. As per the control of the switch by the PWM signals the inductor acts against the input voltage. The DPWM design involves digital circuits like adders, flip-flops, multiplexers, counters and shift registers. DPWM has advantages like easy design, high accuracy, low area and low power consumption. High resolution digitally controlled DC-DC buck converter is designed without the use of high frequency clock [1]. FPGA based implementation of the DPWM is very simple comparatively consuming of few memories, multipliers and adders [2]. DPWM architecture developed with FPGA implies high reliability, linearity and low latency [3]. A brushless DC machines can be digitally controlled by FPGA implementation with no additional hardware and hence has low design complexity [4]. A DPWM technique in [5] gives consistent offtime and on-time control under heavy load and light load conditions with reduced switching losses. FPGA based high resolution DPWM designed using a digital clock manager and I/O delay elements have low cost and higher clock frequency [6]. In this work, the performances of the DC-DC buck converter with the DPWM as voltage regulator is analyzed. # II. Dc -Dc Buck Converter The closed loop DC-DC buck converter with the proposed DPI enables the DPWM technique is shown in the Fig. 1. # DC-DC Buck Converter # Analog to Digital Converter AD7266 The output voltage of the buck converter is less than the input voltage and is controlled by the duty cycle "d". The duty cycle "d" is the ratio of the ON period to the total period cycle of the controlling square pulse. # Modified # d = T on T Where "Ton"refers to the ON period. "T" refers to the total time period of the cycle. The operation of the buck converter is related to the duty cycle as given below V out = d. V in Where "d" is the duty cycle. "Vin" is the input voltage of the buck converter. "Vout" is output voltage of the buck converter. The digital switching control has more advantages like easy designing, high manipulation power, upgradable, immune to environmental changes, easy debugging. In our work, the FPGA based DPWM DC-DC buck voltage regulator, is implemented which satisfies the demand of low voltage and high current application. ADC is utilized for the purpose of acquiring the feedback values of the DC-DC buck converter into the FPGA. ADC IC AD7266 has Successive Approximation Circuit (SAC) and is used for real time implementation. The FPGA based ADC architecture helps in the evaluation of digital error with high accuracy [7]. The Digital PI (DPI) control algorithm is designed using VHDL coding enables the DPWM. The Modified DPI enabled DPWM (MD-DPWM) generators are implemented by FPGA and found to perform efficiently for the disturbances and component variation. The AD7266 is provided to access the analog value in the form of digital equivalence (2N). # III. Digital Pulse Width Modulation Methods The Digital Pulse Width Modulated (DPWM) signal is generated using logical design. The DPWM is generated by three methods. They are i) Counter DPWM method. (CDPWM) ii) Delay line DPWM method. (DDPWM) iii) Hybrid DPWM method. (HDPWM) Using ModelSim, the three DPWM methods are simulated. From the simulated results, the HDPWM generator is found to be advantages when compared to the CDPWM and DDPWM. The CDPWM require high frequency system clock and thus has high power consumption. The DDPWM occupies more area increasing the cost. The relationship of the clock frequency and the switching frequency for the DPWM generator is Resolution refers to the number of bits used in the design. In this work, the three MD-DPWM generators are designed using 2 11 bit resolution. The MD-CDPWM generator uses a 2 11 bit (2047 count) counter. The MD-DDPWM generator uses the 2048:1 multiplexer. The MD-HDPWM generator uses 2 11 bit resolution in which 2 5 bit is used for the MD-DDPWM generation part and 2 6 bit is used for the MD-CDPWM generation part. The frequency of the DPWM generator is 12.5 KHz in the hardware due to the limitations in frequency range with the laboratory prototype. To achieve this frequency, the VHDL coding utilizes the scaled value given by the formula. F CLK = F SW x 2 n F SW - # Scaled_value = 1 2 n X Output frequency X Clock period Where Clock period is 100 ns Output frequency is 12.5 KHz # V. HARDWARE DETAILS The Xilinx Spartan 3A DSP FPGA is used for the design of the DC-DC buck type voltage regulator using MD-HDPWM. The Xilinx Spartan 3A DSP has IC AD7266 for the design of ADC. The set point variations are provided by the two variable push switches. The 16*4 LCD display is activated by the VHDL code. The VHDL codes for the DPI and ADC are designed with 10 times of the actual values to accomplish the FPGA requirements. This scaling is done to make sure that the fractional changes of the ADC and DPI are considered in the design, as the Xilinx Spartan 3A DSP kit do not support the float value implementation. The AD7266 is 8 channels SAR ADC with IC which operates from 2.7V to 5.25V of supply. The ADC performs two functions of sampling and conversion of two channels simultaneously. These conversion values are concurrently accessible in separate data lines. When operated at 3V, the AD7266 gives a throughput rate of 1.5 MSPS with maximum power dissipation of 11.4 mW. Thus low power consumption for high throughput is achieved. The AD7266 has zero pipeline delay; since the sampling control of the two SAR ADCs are accurate. The ADC has two input ranges like 0V to VREF and 2*VREF # VI. RESULTS AND DISCUSSIONS the set-point change and Fig. 13 shows experimental DSO output for the positive and negative line disturbances. Fig. 14&15 indicate the performance of the MD-HDPWM based DC-DC buck converter in closed loop with load disturbances from 445? to 595? and 595? to 445? respectively. The set point is 10 V and input voltage is 20V. The settling time measured during the negative load disturbance with MD-HDPWM seems to be very minimal. Fig. 16&17 show the experimental DSO response of load disturbance from 445 ? to 595? and from 595? to 445? respectively for the MD-HDPWM in closed loop. Fig. 18 shows experimental output response when the load is changed from 470 ? to 495? and from 495? to 470? using MD-DDPWM. Fig. 19 shows experimental output for the negative load disturbance from 445? to 295? using MD-DDPWM. The RTL schematic for the MD-HDPWM technique is presented in Fig. 20. Fig. 21,22,&23 show the design utilization chart for the MD-CDPWM, MD-DDPWM and MD-HDPWM respectively. The experimental setup of DC-DC buck converter using the Xilinx Spartan 3A DSP is shown in Fig. 24. # VII. COMPARISON AND ANALYSIS Table I shows that the Modified DPI enabled HDPWM has lower steady state error and low settling time for the step change variation. The peak overshoot percentage is also less in MD-HDPWM. Table I # b) Experimental Results The simulation outputs of the MD-DPWM generator using the above mentioned three techniques are given below in Fig. 4,5,&6 using ModelSim. The open loop response under line disturbance for the DC-DC buck converter is given for the three MD-DPWM techniques in Fig. 7(a),(b)&(c). Fig. 8(a),(b)&(c) depict the open loop response under load disturbance for the DC-DC buck converter for the three MD-DPWM techniques. Fig. 9 show the start-up transient response along with the set-point variation of closed loop DC-DC buck converter using MD-HDPWM. The CSV file format is plotted using excel sheet format. The time transient parameters like settling time (t s ), rise time (t r ), delay time (t d ), peak time (t p ) and overshoot percentage (%MP) are also calculated and displayed in the graph. The input voltage is 20V.The set point variation is from 11V to 12.8 V for MD-HDPWM. Fig. 10 shows the analysis for the closed loop response under increased line disturbance from 10.4V to 12V and Fig. 11 shows the analysis for the closed loop response under decreased line disturbances from 10.4V to 8.8V for the MD-HDPWM technique. The line voltage in this work are suddenly increased from 18V to 20V and decreased from 20V to 18V. Timing performance indices of the hybrid method are found to have less settling time comparatively and hence hybrid is selected. Fig. 12 shows experimental DSO response for # VIII. CONCLUSION Simulation results show the possibilities of achieving high switching frequency up to 16MHz DPWM. Hardware results show the feasibility of the proposed technique for the available prototype model in our laboratory and found to be satisfactory. The Modified DPI enabled DPWM generators also perform voltage regulation of the power supply. The FPGA based Modified DPI enabled Hybrid based DPWM voltage regulator is found to be immune to circuit component variations, and also to line-load disturbances. 1![Fig.1: Closed loop DC-DC Buck Converter with MD-DPWM control](image-2.png "Fig. 1 :") ![Switching frequency F CLK -Clock frequency 2 n -Resolution in bits In this work, the design of the Modified DPI enabled DPWM using 2 11 -bit resolution is used which yields F SW of 12.5 KHz and achieved the F CLK of 21 MHz Hybrid DPWM generator is the combination of both counter based DPWM and delay-line based DPWM methods. The DC input signal of 2 11 -bit resolution is bit split into 2 5 -bit and 2 6 -bit resolutions. In which 2 5 -bit resolution is used for the generation of the DDPWM and 2 6 -bit resolution for the generation of the CDPWM generation. The HDPWM has two set of SET and RESET signal (each from CDPWM and DDPWM generations) which are logically ANDed to give a SET and RESET signal for the SR-flip-flop are shown in Fig.2.](image-3.png "") 23![Fig. 2: SIMULINK-MATLAB block of Hybrid based DPWM IV. THE PROPOSED METHOD: MODIFIED DPI ENABLED DPWM GENERATOR The modified DPWM generator utilizes the DPI controller to manipulate the duty cycle proportionate to the error as well as enable the DPWM generator. Real time feedback equivalence value of 0 to 5V is selected by the VHDL coding and fed to the ADC for processing. gain parameters are k p =0.6 and k i =0.055. The DPI controller values are made visible by interfacing the 12 LEDs of the FPGA. The increase and decrease push buttons available in the FPGA kit is also activated for varying the voltage reference value. These push switch values are coded along with the limiter. These values are interfaced with the LCD display of the FPGA in order to monitor the variable set values and the settling values. Initially the set value is maintained at 10V by default in](image-4.png "Fig. 2 :Fig. 3 :") ![also show that MD-HDPWM used with the closed loopDC-DC buck converter has less settling time and rise time when compared to the other two like MD-CDPWM and MD-DDPWM methods. TableII& III show the settling time for both the positive and negative line disturbances are good for the MD-HDPWM. TableIVshows that the MD-HDPWM has lower area utilization in FPGA device compared to the MD-DPWM and also the clock frequency of the MD-HDPWM is less in comparison of the MD-CDPWM. Thus the modified DPI enabled HDPWM method is cost effective in comparison with the other methods.](image-5.png "") 4![Fig. 4: Counter based DPWM generated in ModelSim](image-6.png "Fig. 4 :") 56![Fig. 5: Delay line based DPWM generated in ModelSim](image-7.png "Fig. 5 :Fig. 6 :") 7891020171114161819![Fig. 7: Open loop deviated response of DC-DC buck converter with line disturbance using a) MD-CDPWM. b) MD-DDPWM. c) MD-HDPWM](image-8.png "Fig. 7 :Fig. 8 :Fig. 9 :Fig. 10 : 2017 F©Fig. 11 :Fig. 14 :GlobalFFig. 16 :Fig. 18 :Fig. 19 :") 1MethodMD-CDPWMMD-DDPW MMD-HDPWMSettling Time (ts)4.716.25.1Rise Time (tr)0.0350.0020.0419Delay Time (td)0.0320.0230.0385Peak Time (tp)0.040.030.164Table for MD-CDPWM in Xilinx Spartan 3A FPGA Fig. 22: Design Utilization Table for MD-DDPWM in Xilinx Spartan 3A FPGAFig. 23: Design Utilization Table for MD-HDPWM in Xilinx Spartan 3A FPGA Fig. 24: Experimental setup for the Modified DPI enabled DPWM based DC-DC buck converter using FPGA 2Increased Line DisturbanceMethodsMD-CDPWMMD-DDPWMMD-HDPWMRise Time in s (tr)0.20.30.2Time Delay in s (tp)0.10.10.1Settling Time in s (ts)3.82.71.6Percentage Overshoot(%MP) 14.286%17.647%15.38%Output Voltage Ripple0.040.040.03846Initial Value before disturbance9.8 V10.2 V10.4 VPeak Value at disturbance11.2 V12 V12 VMethodsMD-CDPWMMD-DDPWMMD-HDPWMRise Time in s (tr)0.20.20.23Time Delay in s (tp)0.1420.1350.13Settling Time in s (ts)3.262.822.62Percentage Overshoot (% MP)14.2857%13.725%15.38%Output Voltage Ripple0.040.040.04Initial Value before disturbance9.8 V10.2 V10.4 VMinimum Value at disturbance8.4 V8.8V8.8 VMethodsMD-CDPWMMD-DDPWMMD-HDPWM2 11 =2 6 +2 5Resolution with specification2 11 -bit Counter Designed2 11 2048 : 1 Mux Designed(2 6 -bit Counter & 32:1 MuxDesigned)Number of Sliced Flip Flops6652716697Number of 4 input LUTs163326701657Number of occupied slices109036591130Number of bonded IOBs374137Average Fan-outof Non-clock2.962.592.95nets 3 4F © 2017 Global Journals Inc. (US) Year 2017 F © 2017 Global Journals Inc. (US) © Global Journals Inc. (US) © 2017 Global Journals Inc. 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