# I. Introduction all Grid Array (BGA) is a type of surface-mount packaging for integrated circuits (IC) in which the chip device at the printed circuit board (PCB utilizes the connection of square grid array of solder balls. Generally, BGA is much more advantageous compared to Pin Grid Array (PGA) and Chip-scale Package (CSP), in terms of reliability, durability and manufacturability [1].In contrast, Multi-stack BGA device is a renovated design of conventional BGA flip chip, aimed to multiply the performance of device by slightly sacrificing its height while still retaining its small compact structure. Various researches on the structural and underfilling flow aspects in the multi-stack chip device have been extensively conducted [2 -5]. The underfill encapsulation process is of utmost important to enhance the package reliability as well as serve as protection to the flip chip device. Moreover, it may also act as heat sink to dissipate thermal stress away from the solder joints [6].The manufacturing process involving underfill process must be properly considered and designed to achieve highest state of reliability. In achieving this target, the underfilling process of multi-stack BGA or generally the BGA flip chip devices usually suffer problems relating to extended filling time and incomplete filling. These defects are generally undesirable which critically impart the quality of the encapsulation process. Subsequently, this will lengthen the lead time and incur additional manufacturing costs. The optimization studies of underfilling flow through BGA device have been comprehensively studies by Aizat et al., from various aspects namely encapsulant dispensing methods, bump orientation and sizes [7 -9]. They concluded that the U-type dispensing method and perimeter bump arrangement yields the shortest filling time. It is usually a practice in industry to pre-heat the chip device at about 60°C ? 80°C prior to the underfilling process. The aim however is to ensure the encapsulant does not solidify before the curing process [6]. Several experimental and numerical simulation researches have been carried out to investigate the thermal properties of the stacked chip device, from the perspective of heat power dissipation [10], effective thermal coefficient [11] and heat distribution in the package [12]. These studies have emphasized the particular importance of temperature in optimizing the underfill encapsulation process. Previous literatures showed that the underfill process can to be optimized through proper introduction of heat to the different layers of the package. Therefore, a simple comparative study is required to justify the influence of temperature on the underfill flow for multi-stack BGA device based on scaleup experimental model. This scaled-up BGA model has been utilized by various researchers [3 -5, 7 -9] and proven viable in improving the visualization of the encapsulant flow through the solder bumps that is similar to the actual industrial setup. To date, no comparative study has been carried out to identify the contribution of thermal energy to accelerate the encapsulant flow in multi-stack BGA device using experimental approach. Essentially, this paper is aimed to provide useful information for the manufacturer in an attempt to optimize the underfill process using thermal approach. # II. Methodology A scale up model of multi-stack BGA was constructed using clear Perspex and plastics beads. Several considerations were made during the design process of the experimental setup and after countless of iterations and improvements, the final design of the experimental setup will rely on four walls that is confined around the multi-stacked BGA. This setup will mimic industrial barrier used in encapsulation process to prevent spillage of the fluid outside the integrated chip (IC) package. The advantages of such barrier set up is to ensure simultaneous flow of fluid into all layers of the multi-stacked BGA model, as well as to minimize the waste of underfilling fluid due to spillage and overflow [13]. The barrier and three BGA plate models were constructed using clear Perspex and plastic beads that is jointed together using super glue. Excess glue strains on the Perspex were removed for better appearance and smoother surface to eliminate future possible sources of error. Figure 1 Each BGA model plate is then immersed in hot water bath at 70°C for around 20 seconds to reach thermal equilibrium. After being soaked in hot water, a dry cloth is used to remove some of the excess water from the BGA plate. The heated plates were then carefully put into the barrier that is stacked on top of each other. Two videos cameras were used to record the flow of fluid across the multi-stack BGA in both top and side views simultaneously. Later, non-Newtonian fluid with similar fluid properties was used to mimic the industrial encapsulant. The encapsulant were carefully poured into the inlet of barrier to enable it flows into the multi-stack BGA. The replacement fluid is poured thoroughly at constant rate so that it is able to flow in at each layers without any spillage or bubble formation inside the encapsulant. Afterwards, the videos obtained were analyzed and the filling times for the encapsulant to attain filling of 20%, 40%, 60%, 80% and finally the completion 100% at each layers were tabulated and presented in suitable graphical forms. # III. Results and Discussions There are total of two distinct sets of experiments with varying parameter scarried out to justify the impact of thermal on the underfill encapsulant flow through the BGA. The main difference between these set sis depicted as follow: Set A: Reference set with all three layers at room temperature of 25°C Set B: Pre-heated set with all three layers at 70°C The video recordings of the underfill flow through the BGA are analyzed and subsequently the results of the filling time at certain filling percentage for both experimental sets A and B were tabulated in Table 1(i) and Table 1(ii) respectively. Subsequently, a corresponding filling time plot is constructed and presented in Figure 2. Similar procedures were being used to study the encapsulant flowin the BGA at normal conditions without introducing heat energy. This experiment is repeated with a pre-arranged three layers of BGA layers at room temperature without adding heat on it. (ii) Set B at elevated temperature of 70°C By comparing the filling times for both experimental sets in Table 1(i) and Table 1(ii), it appeared that the flow tends to be faster a tall three layers of Set B. Thus, the filling time gap between top and middle layers were reduced and all three layers appeared to have almost similar flowing rate. So it is deduced that the increase in underfilling temperature willincreases the flow rates of the underfilling mold. The underfillflow rate appeared to be inconsistent throughout the whole underfilling process. From Figure 2, the encapsulant generally flows faster at the beginning and the flow rate reduces near completion. This is essentially due to the cumulative solder bump resistance that gradually built up as the encapsulant advances. Nonetheless, it can be approximated that the average flow rate of the underfilling process can be approximated through gradient calculation for the whole segment of the graph. The average flow rate, ?? ? is in fact inversely proportional to the gradient of the graph and can simply be approximate dusing the formula: ?? ? = 0.8 ?? , with?? being the time taken for the encapsulant flow from 20% filling until 100% filling. # IV. Conclusion Based on the comparative experimental study conducted, it was shown that the introduction of thermal energy had increased the overall encapsulant flow rate across all layers of the multi-stack BGA with an averagely of 75.2% upon comparison with the standard setup at normal condition. Therefore, it is justified that the temperature has played a significant role in accelerating the underfill encapsulation process. The BGA flip chip is required to be heated to a sufficient high temperature prior the commencement of underfilling process. This will ensure substantial filling rate and prevent the solidification of the underfill mold. Additionally, this research has also provided some insights regarding the trend of underfill flow across multi-stack BGA regardless of its thermal source. The encapsulant tends to flow faster at the bottom layer followed by middle layer and lastly the top layer. It was also shown that the underfill flow also gradually decelerates as it progresses through the array of solder bumps towards the outlet vent. ![Ng ? , Aizat Abas ? , MHH Ishak ? & MZ Abdullah ? Author ? ? : School of Mechanical Engineering, Engineering Campus, ? ?](image-2.png "BFeiChong") ![depicts the schematics diagram of the experimental setup being used to study the flow of the underfill fluid across a multi-stacked BGA model.](image-3.png "") 1![Figure 1: Multi-stack BGA model confined inside a barrier.](image-4.png "Figure 1 :") 2![Figure 2: Comparison plot of filling time for experiment set A (dashed line) and set B (solid line).](image-5.png "Figure 2 :") 3![Figure3depicts the comparison of the flow front advancement for both Set A and Set B at specific filling intervals of 20%, 40%, 60% and 80% based on the encapsulant flow at the top layer. It appeared that the encapsulant flow fronts are similar across both setups inferring that it is invariant to the under fill temperature condition. Upon careful consideration, based on the encapsulant flow from the side view, the increase in temperature produces a more uniform flow along the multi-stack BGA across all three layers.](image-6.png "Figure 3") 3![Figure 3: Comparison of the encapsulant flow as seen from top and side views for experiment (i) Set A and (ii) Set B based on the filling percentage of flow at the top layer.](image-7.png "Figure 3 :") 1(i) Set A at room temperature of 25°CLayers20%Filling time at different filling percentages (s) 40% 60%80%100%Top144278120170Middle12265394125Bottom817356398 2LayerAverage Flow Rate, ?? ? (s -1 ) Set A (At 25°C) Set B (At 70°C)Top5.128 × 10 ?39.091 × 10 ?3Middle7.080 × 10 ?312.50 × 10 ?3Bottom8.889 × 10 ?315.38 × 10 ?3Average7.032 × 10 ?312.32 × 10 ?3 © 2016 Global Journals Inc. (US) © 2016 Global Journals Inc. (US) ° ## V. Acknowledgments The work was partly supported by the FRGS grant FRGS/1/2015/TK03/USM/03/2 and Short Term Grant 60313020 from the Division of Research and Innovation, UniversitiSains Malaysia. * Plastic ball grid array (PBGA) overview JJLiu HBerg YWen SMulgaonker RBowlby AMawer Mater. Chem. Phys 40 1995 * Stacked solder bumping technology for improved solder joint reliability XingshengLiu ShuangyanXu Microelectronics Reliability 2001 41 * Fluidstructure interaction analysis on the effect of chip stacking in a 3D integrated circuit package with through-silicon vias during plastic encapsulation ESErnest MZOng CYAbdullah Khor Microelectronic Engineering 113 2014 * Analysis of encapsulation process in 3D stacked chips with different micro bump array ESErnest MZOng CYAbdullah Khor International Communications in Heat and Mass Transfer 2012 39 * Effects of outlet vent arrangement on air traps in stacked-chip scale package encapsulation DRamdan MZAbdullah 2012 39 International Communications in Heat and Mass Transfer * Chapter 3 -Encapsulation Process Technology, Encapsulation Technologies for Electronic Applications HArdebili MGPecht 2009 Elsevier * Effect of ILU dispensing types for different solder bump arrangements on CUF encapsulation process AizatAbas MSHaslinda MH HIshak ASNurfatin MZAbdullah FCheAni Microelectronic Engineering 2016 * Lattice Boltzmann Method of Different BGA Orientations on I-Type Dispensing Method AizatAbas MhhGan Ishak PLoS ONE 11 7 e0159357 2016 * Lattice Boltzmann and finite volume simulations of multiphase flow in BGA encapsulation process AizatAbas MhhAbdullah Ishak ARPN Journal of Engineering and Applied Sciences 2015 * Thermal conductivity of single and multi-stacked DI-BSCCO tapes TomoyukiNaito HiroyukiFujishiro Cryogenics 49 2009 * Thermal resistance of side by side multi-chip package: Thermal mode analysis Dao-LongChen Tei-ChenChen Microelectronics Reliability 2015 55 * Impact of die thinning on the thermal performance of a central TSV bus in a 3D stacked circuit SamsonMelamed Fumitoimura Microelectronics Journal 2015 * Effect of thermo capillary action in the underfill encapsulation of multi-stack ball grid array ChongFei AizatNg MhhAbas Ishak AbdulAbdullah Aziz Microelectronics Reliability 2016