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\title{Energy Efficient FMA for Embedded Multimedia Application}
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\begin{document}

             \author[1]{Mandala Rakesh  Raj}

             \author[2]{Ms S.  Sujana}

             \affil[1]{  VARDHAMAN COLLEGE OF ENGINEERING}

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\date{\small \em Received: 6 December 2013 Accepted: 2 January 2014 Published: 15 January 2014}

\maketitle


\begin{abstract}
        


This article presents energy efficient fused multiplyadd for multimedia applications. Low cost, low power and high performance factors diddle the design of many microprocessors directed to the low-power figuring market. The floating point unit occupies a significant percentage of the silicon area in a microprocessor due to its wide data bandwidth and the area occupied by the multiply array. The fused floating-point multiply-add unit is utilitarian for digital signal processing (DSP) applications such as fast Fourier transform (FFT) and discrete cosine transform (DCT). The proposed designs are implemented for single precision and synthesized with a 45-nm standard cell library. To improve the performance of the fused floating point multiply-add unit, we are supervening upon leading zero anticipation with the novel leading zero detection, as the novel leading one detection algorithm allowing us to significantly reduce the anticipation failure rates.

\end{abstract}


\keywords{floating point, binary128, fused multiply add, simd, implementation, computer arithmetic.}

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\let\tabcellsep& 	 	 		 
\section[{Introduction}]{Introduction}\par
his paper presents energy efficient fused multiplyadd unit for multimedia applications. In this, floating point can be implemented by using different precisions. As we have SP (Single Precision), DP (Double Precision), QP (Quadruple Precision). IEEE Binary 32 which is pertained as single precision and binary64 referred to as double precision. Floating-point operations have both gained widespread popularity in versatile multimedia and scientific applications, resulting in modern processors patronize both the precisions. Due to accumulation errors in computations they are becoming deficient for today large-scale applications. This precision problem can be overcome by one promising approach that is by using the binary 128 which is referred to as quadruple precision or QP format. The accuracy and numerical stability of many applications can be improved by introducing this format and is already specified in the new IEEE-754-2008 standard. Another approach to which we have to improve the performance is using the fused multiply add (FMA) operation which yields one rounding error for two operations \hyperref[b3]{[3]}. The first FMA is introduced in the year 1990 by IBM RS/6000 \hyperref[b6]{[6]}, \hyperref[b7]{[7]}. After FMA is implemented by several companies like HP, MIPS, ARM and Intel.\par
Many algorithms are developed on floating-point fused multiply add unit to decrease its latency \hyperref[b1]{[2]}, \hyperref[b4]{[4]}. As we can say it is a key feature of the floating-point unit because it greatly increases the floating-point performance and accuracy since rounding is performed only once for the result.\par
A Field Programmable Gate Array, FPGA provides a versatile and inexpensive way to implement and test VLSI designs. It is mostly used in low volume applications that cannot afford silicon fabrication or designs which require frequent changes or upgrades.\par
In FPGA's, the bottleneck for designing efficient floating-point units has mostly been area with advancement in FPGA architecture \hyperref[b3]{[3]}, there is a significant increase in FPGA densities so latency has been the main focus of attention in order to improve performance.\par
The main contribution and objective of our work is to implement the architecture which is proposed by Lang/Bruguera but with little change to facilitate the implementation.\par
In reminder of this paper is organized as follows. Proposed FMA unit section 2 backgrounds, section 3 proposed methods and section 4 describes its general architecture. Section 5 provides the evaluation results and Section 6 concludes this paper. 
\section[{II.}]{II.} 
\section[{Background}]{Background}\par
In this paper, the floating-point fused multiplyadd operation A x B + C is implemented for the IEEE floating-point format. In this format, a floating-point number X represents the valuep e s f X ? × × ? = ? ) 1 (\par
, Where s , f , ? ,e ,and p are integers with s being the sign bit; f the normalized mantissa; ? the radix, 2 for binary; e the biased exponent; and p the biased number.\par
The fused multiply-add unit gets the input operands A, B, and C with valuesea a sa f A 2 . . ) 1 (? = , eb b sb f B 2 . . ) 1 (? = and ec c sc f C 2 . . ) 1 (? =\par
and performs the fused multiply-add operation:) 2 . . ) 1 ( 2 . . ) 1 (( ec c sc eb ea b a sb sa f f f rnd C B A ? + ? = + × + ?\par
Where the computed fused multiply-add result is rounded and normalized. The FMA architecture proposed before implemented in several floating-point ? Inorder to reduce the latency, the bit inversion and alignment of the significand of A is done in parallel with the multiplication \hyperref[b1]{[2]}. The bit inversion provides the one's implement of A for an effective subtraction.\par
? The shift amount of the alignment depends on the value of d = E a -(E b + E c ), where E a, E b , E c are the exponents of the A, B, and C operands, respectively.\par
? When d ? 0 (i.e. E a > (E b + E c )), in a conventional alignment, B x C would have to be aligned with a right shift of d bits. vectors that are reduced together with the aligned A using 3:2 CSA, because the product has only 106 bits. The 55 most-significant bits will be sign extension bits, for theses 55 most significant bits, we use two multiplexers, one to select between A and inverted A as a sum vector and the second one to select between zeros and A as a carry vector by Xor-ing sign extension bits then the outputs of the two multiplexers are concatenated at the output of the CSA to obtain the 161-bit sum and carry words. c) The next step is the addition of the carry and sum words and the determination of the shift amount for normalization.\par
? The carry and sum words, obtained at the output of the CSA, are added in a 161-bit one's complement adder (with end around carry adjustment for effective subtraction). As the result can be negative, a complementer is required at the output of the adder.\par
? In parallel with the significands addition, the normalization shift is determined. The LZA (Leading Zero Anticipator) \hyperref[b12]{[12]} produces the amount of the shift directly from the operands. d) Once the result of the addition is obtained, the normalization shift can be performed since the shift amount has been already determined. A normalization shift is required to place the mostsignificant bit of the result at bit 0; as a consequence, normalization is performed to compensate for the cancellation produced in subtraction as well as to compensate for the way the alignment is performed. With this scheme, the delay of the FMA operation is determined by the sum of the delays of the following components: multiplier, 3-2 CSA, 161-bit adder plus complementer, normalization, and rounding. On the other hand, the main hardware components are: multiplier, alignment shifter, 3:2 CSA, LZA, 161-bit adder, normalization shifter, and rounder. 
\section[{III.}]{III.} 
\section[{Proposed Architecture}]{Proposed Architecture}\par
We now describe the proposed FMA architecture. Since the unit is quite complex, we present this description in a single step. In this section, we give an overview of the scheme, with just enough detail to make it understandable and believable. Here we use Fig. \hyperref[fig_3]{2} to illustrate the description.\par
The objective of the proposed FMA architecture is to reduce the overall delay, and Power. Since, in floating-point addition and multiplication, one of the approaches to reduce latency has been to combine addition with rounding \hyperref[b5]{[5]}, \hyperref[b10]{[10]}, \hyperref[b12]{[12]}, \hyperref[b13]{[13]}, we follow the same approach. For this approach, in floating-point addition and multiplication, the order of normalization and rounding is interchanged. This seems impractical to do for FMA because, before the normalization, the rounding position is not known. The solution we explore is to perform the normalization before the addition.  
\section[{Architecture}]{Architecture}\par
To improve the performance of the fused floating point multiply-add unit, we are supervening upon leading zero anticipation with the novel leading zero detection, as the novel leading one detection algorithm allowing us to significantly reduce the anticipation failure rates. The proposed leading digit is worked using tree structure, where inputs of n bits are divided into n/2 pairs of bits.\par
For each pair of bits a two bit count is generated and another counter is triggered to calculate the depth of the tree. For example a four digit can be paired into two pairs and a counter is used to find the one/ zero in pair i and i+1 and the second counter is used to find the value of required bit in which pair and at which level. This method is continued of log 2 (n) levels.\par
To boost this tree structure we use a structure method which speed's up by a 4 bit or even 8bit to reduce the hierarchy of the tree structure. 
\section[{IV.}]{IV.}\par
Detailed Description of some Modules of the Architecture a) 3:2 CSA The multiplier produce 106-bit sum and carry vector that are reduced together with the aligned A using 3:2 CSA. Although the output of the multiplier must be positive number because we multiply two positive numbers (sign and magnitude representation), one of the two output vectors of the multiplier may be negative because of using booth algorithm which use negative sets \{-1,-2\} which convert a positive number with sign and magnitude representation to a negative number with two's complement representation. The addition of sum and carry vectors must be a positive number but one of them, not both, may be negative.\par
Instead of using 161-bit CSA, only the 106 leastsignificant bits of the aligned A are needed as input to the 3:2 CSA, because the product of sum and carry vectors has only 106 bits and The 55 most-significant bits will be sign extension bits which have two cases \{0, 0\} if both sum and carry vectors are positive or \{0, 1\} if one of them is negative. For the 55 mostsignificant bits, we use two multiplexers, one to select between A and inverted A as a sum vector and the second one to select between zeros and A as a carry vector by Xor-ing sign extension bits then the outputs of the two multiplexers are concatenated at the output of the CSA to obtain the 161-bit sum and carry words. 
\section[{b) Leading zero Anticipator}]{b) Leading zero Anticipator}\par
The leading zero anticipator (LZA) has two main parts: the encoding of the leading-one position i.e. detection module and the correction of this position i.e. correction module. The detection module are divided into two parts the first one is called LZA and it determines the number of leading zeros i.e. the position of the leading one. By producing a string of zeros and ones where the position of the most significant 1 is the Year 2014 J position of the leading one. The second part, called leading zero detectors (LZD), counts the number of zero digits from the left-most position until the first nonzero digit is reached i.e. leading one position. Since the detection is done from most significant bit to least significant bit regardless of the carry that may come from the least significant bit, the detection of leading one position may be off by one bit. The LZA logic takes two input strings and uses a set of logical equations given below.\par
After LZA logic LZD is used to drive the normalization shifter \hyperref[b11]{[11]} by encoding the position of leading one to its weighted binary representation.0 ), . . ( ) . . ( 1 1 1 1 1 1 > + ? + × = + + + + + + i g g z z t g z z g t f i i i i i i i i i i i 1 0 0 .t t f = Where i i i b a t ? = i i i b a g . = i i i b a z . =\par
The LZD unit assumes n bits as input and produces log 2 n bits of the leading one position Pattern Position Valid  The IEEE 754 binary floating-point standard defines a set of normalized numbers and four sets of special numbers. Of the four types of special numbers, three do not require computation for arithmetic operations. These include Not-a-Numbers (NaN), infinities, and zeros. De-normalized numbers, also known as subnormal or denormals are the fourth type of special number and do require computation.\par
Normalized numbers can be described by the following:bias xe xs f X ? × × × ? = 2 1 ) 1 (\par
Where X is the value of the normalized number, X s is the sign bit, X f is the fractional part of the significand, Xe is the exponent, and bias is the bias of the format which corresponds to 127, 1,023, and 16,383, for single, double, and quad, respectively. Denormalized numbers can be described by the following:0 , 2 0 ) 1 ( 1 ? × = × × × ? = ? f i X f X e bias xs\par
The denormal format differs from a normal number in that there is no implied bit and the exponent is not equal to X e -bias, but , instead, is forced up by 1 to E min , which is equal to -126, -1,022, and -16,382, depending on the format.\par
Using the results from the LZD, the result from the adder is shifted left to normalize the result. That means now the first bit is 1.\par
The normalize is mostly a large shifter. The shifter has more than one stage. The stages are organized from the coarsest to the finest. The last stage performs a shift by one or two due to correction signal. This should have a negligible effect on the delay of the last stage. 
\section[{d) Rounding}]{d) Rounding}\par
The IEEE 754 floating-point standard has been widely adopted since its introduction in 1985. The standard requires that all arithmetic operations are rounded so as to maintain as high a degree of accuracy and uniformity across different computing platforms as possible. The rounding decision is taken by knowing also sticky and round bits. The sticky bit is calculated from the result by OR-ing all least significant bits after the round bit. Rounding operations were originally viewed as a final separate step in most arithmetic circuit implementations. This has been merged with the carrypropagate addition in floating-point adders by delaying normalization until after rounding. Four different rounding modes are laid down by the IEEE floating-point standard \hyperref[b8]{[8]}, \hyperref[b9]{[9]}: rounding toward 0, rounding to nearest (even), and rounding to ± . Rounding to nearest (even) is the standard's default mode; rounding toward zero is helpful in many DSP applications; and rounding to ± is used in interval arithmetic, which affords bounds to be specified on the accuracy of a number.  
\section[{J e XIV Issue VI Version}]{J e XIV Issue VI Version}
\begin{quote}
I V. Simulations Results\end{quote}
 
\section[{b) Power}]{b) Power}\par
The power is the important aspect of the any architecture as the power decreases the power consumption of the entire processor decreases. In this project the power of the both proposed and the previous architecture are calculated using Cadence RC complier in different TSMC standard libraries. The proposed architecture is efficient in terms of power.  
\section[{Conclutions}]{Conclutions}\par
Architecture for a floating-point Multiply-Add-Fused (FMA) unit that reduces the latency of the traditional FMA units has been proposed. The proposed FMA is based on the combination of the final addition and the rounding, by using proposed LZD. This novel leading one detection algorithm allowing us to significantly reduce the anticipation failure rates. We embedded the proposed technique in Fused floating point multiply and Accumulation unit and its silicon area and performance with other existing solution. This approach has been used previously to reduce the latency of the floating-point addition and multiplication. However, it can be used only if the normalization is performed after the rounding and this is not possible for the FMA operation because the rounding position is not known until the normalization has been performed. To overcome this difficulty, we propose that the normalization be carried out before the addition. This required a careful design of some other parts of the FMA, the leading-zeros-detector (LZD).\begin{figure}[htbp]
\noindent\textbf{2014}\includegraphics[]{image-2.png}
\caption{\label{fig_0}T © 2014}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{1}\includegraphics[]{image-3.png}
\caption{\label{fig_1}Fig. 1 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-4.png}
\caption{\label{fig_2}Je}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{2}\includegraphics[]{image-5.png}
\caption{\label{fig_3}Fig. 2 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-6.png}
\caption{\label{fig_4}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{3}\includegraphics[]{image-7.png}
\caption{\label{fig_5}Fig. 3 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{456}\includegraphics[]{image-8.png}
\caption{\label{fig_6}Fig. 4 :Fig. 5 :Fig. 6 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{II} \par 
\begin{longtable}{P{0.5335106382978723\textwidth}P{0.18085106382978722\textwidth}P{0.13563829787234044\textwidth}}
Methods\tabcellsep Area\tabcellsep Power\\
Using-nm\tabcellsep (µm²)\tabcellsep (mW)\\
Existing\tabcellsep 87,908\tabcellsep 19\\
Method(90nm)\tabcellsep \tabcellsep \\
Proposed\tabcellsep 6,984\tabcellsep 6.35\\
Method (45nm)\tabcellsep \tabcellsep \\
VI.\tabcellsep \tabcellsep \end{longtable} \par
 
\caption{\label{tab_0}Table II :}\end{figure}
 			\footnote{© 2014 Global Journals Inc. (US)} 		 		\backmatter  			  				\begin{bibitemlist}{1}
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\bibitem[Schmookler and Nowka (2001)]{b11}\label{b11} 	 		‘Leading Zero Anticipation and Detection --A Comparison of Methods’.  		 			M Schmookler 		,  		 			K Nowka 		.  	 	 		\textit{Proceedings of the 15th IEEE Symposium on Computer Arithmetic},  				 (the 15th IEEE Symposium on Computer ArithmeticVail, Colorado)  		June 2001. p. .  	 
\bibitem[Santoro et al. ()]{b9}\label{b9} 	 		‘Rounding Algorithms for IEEE Multipliers’.  		 			M R Santoro 		,  		 			G Bewick 		,  		 			M A Horowitz 		.  	 	 		\textit{Proc. IEEE Ninth Symp. Computer Arithmetic},  				 (IEEE Ninth Symp. Computer Arithmetic)  		1989. p. .  	 
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\bibitem[Montoye et al. (1990)]{b7}\label{b7} 	 		‘Second -Generation RISC Floating Point with Multiply-Add Fused’.  		 			R Montoye 		,  		 			E Hokenek 		,  		 			S Runyon 		.  	 	 		\textit{IEEE journal of solid-state circuits}  		October 1990. 25  (5)  p. .  	 
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\end{document}
