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\def\makelabel##1{\upshape ##1}}% } {\end{list}\end{raggedright}} \newenvironment{specHead}[2]% {\vspace{20pt}\hrule\vspace{10pt}% \phantomsection\label{#1}\markright{#2}% \pdfbookmark[2]{#2}{#1}% \hspace{-0.75in}{\bfseries\fontsize{16pt}{18pt}\selectfont#2}% }{} \def\TheFullDate{2014-01-15 (revised: 15 January 2014)} \def\TheID{\makeatother } \def\TheDate{2014-01-15} \title{Design of Low Power 4-Bit CMOS Braun Multiplier based on Threshold Voltage Techniques} \author{}\makeatletter \makeatletter \newcommand*{\cleartoleftpage}{% \clearpage \if@twoside \ifodd\c@page \hbox{}\newpage \if@twocolumn \hbox{}\newpage \fi \fi \fi } \makeatother \makeatletter \thispagestyle{empty} \markright{\@title}\markboth{\@title}{\@author} \renewcommand\small{\@setfontsize\small{9pt}{11pt}\abovedisplayskip 8.5\p@ plus3\p@ minus4\p@ \belowdisplayskip \abovedisplayskip \abovedisplayshortskip \z@ plus2\p@ \belowdisplayshortskip 4\p@ plus2\p@ minus2\p@ \def\@listi{\leftmargin\leftmargini \topsep 2\p@ plus1\p@ minus1\p@ \parsep 2\p@ plus\p@ minus\p@ \itemsep 1pt} } \makeatother \fvset{frame=single,numberblanklines=false,xleftmargin=5mm,xrightmargin=5mm} \fancyhf{} \setlength{\headheight}{14pt} \fancyhead[LE]{\bfseries\leftmark} \fancyhead[RO]{\bfseries\rightmark} \fancyfoot[RO]{} \fancyfoot[CO]{\thepage} \fancyfoot[LO]{\TheID} \fancyfoot[LE]{} \fancyfoot[CE]{\thepage} \fancyfoot[RE]{\TheID} \hypersetup{citebordercolor=0.75 0.75 0.75,linkbordercolor=0.75 0.75 0.75,urlbordercolor=0.75 0.75 0.75,bookmarksnumbered=true} \fancypagestyle{plain}{\fancyhead{}\renewcommand{\headrulewidth}{0pt}} \date{} \usepackage{authblk} \providecommand{\keywords}[1] { \footnotesize \textbf{\textit{Index terms---}} #1 } \usepackage{graphicx,xcolor} \definecolor{GJBlue}{HTML}{273B81} \definecolor{GJLightBlue}{HTML}{0A9DD9} \definecolor{GJMediumGrey}{HTML}{6D6E70} \definecolor{GJLightGrey}{HTML}{929497} \renewenvironment{abstract}{% \setlength{\parindent}{0pt}\raggedright \textcolor{GJMediumGrey}{\rule{\textwidth}{2pt}} \vskip16pt \textcolor{GJBlue}{\large\bfseries\abstractname\space} }{% \vskip8pt \textcolor{GJMediumGrey}{\rule{\textwidth}{2pt}} \vskip16pt } \usepackage[absolute,overlay]{textpos} \makeatother \usepackage{lineno} \linenumbers \begin{document} \author[1]{Dayadi Lakshmaiah} \affil[1]{ CJITS,JANGON,WARNAGAL} \renewcommand\Authands{ and } \date{\small \em Received: 9 December 2013 Accepted: 1 January 2014 Published: 15 January 2014} \maketitle \begin{abstract} A circuit design for a new Low Power 4-bit Braun Multiplier is presented. The multiplier is implemented by using different Threshold Voltage techniques. Power reduction techniques are proposed for 4-bit Braun Multiplier which is designed by Full Adders. To get Optimum design low threshold voltages are used at critical paths similar way high threshold voltages are used at non critical paths. The design uses CMOS digital circuits in order to reduce the power dissipation while maintaining computational throughput. This architecture is simulated at 90nm Technology with 1.2v power supply. The power dissipation of nearly 46%, Power Delay Product of 56% and delay 19.3% has been reduced by using proposed techniques with good performance. \end{abstract} \keywords{braun multiplier, full adder, } \begin{textblock*}{18cm}(1cm,1cm) % {block width} (coords) \textcolor{GJBlue}{\LARGE Global Journals \LaTeX\ JournalKaleidoscope\texttrademark} \end{textblock*} \begin{textblock*}{18cm}(1.4cm,1.5cm) % {block width} (coords) \textcolor{GJBlue}{\footnotesize \\ Artificial Intelligence formulated this projection for compatibility purposes from the original article published at Global Journals. However, this technology is currently in beta. \emph{Therefore, kindly ignore odd layouts, missed formulae, text, tables, or figures.}} \end{textblock*} \let\tabcellsep& \section[{Introduction}]{Introduction}\par n order to achieve the high speed and low power demand in DSP applications Braun's multiplier are broadly used. The Braun's multiplier is generally called as the Carry Save Array Multiplier. The architecture of a Braun's multiplier consists of AND gates and full adders. The prolific growth in semiconductor device industry has been Indicates to the high performance portable systems with enhanced reliability in data transmission. In order to maintain the high performance fidelity applications, emphasis will be on incorporation of low power modules in future system design \hyperref[b0]{[1]}\hyperref[b1]{[2]}\hyperref[b2]{[3]}\hyperref[b3]{[4]}\hyperref[b4]{[5]}. The design of such modules power consumption or dissipation in fundamental arithmetic computation units such as adders and multipliers. This implies a need to design low power multipliers towards the development of efficient power \& high-performance systems. The selection of the most efficient implemented multiplication has continually challenge DSP system designers \hyperref[b5]{[6]}\hyperref[b6]{[7]}. Every system designer offers a wide range of tradeoffs in terms of speed, complexity and power consumption. Input sequences to the multiplier can be fed in parallel, serial or a hybrid (parallel serial) this proposal approaches gives high processing speed. Usually Parallel multipliers are adopted at the expense of high area complexity. \section[{Multiple}]{Multiple}\par parallel multiplications Algorithms (architectures) \hyperref[b7]{[8]} have been proposed to reduce the chip area increase the speed of the multipliers' and reduce the power dissipation using various techniques. Several of these techniques reduce the power dissipation by eliminating spurious transitions in the circuit \hyperref[b8]{[9,}\hyperref[b10]{11]}. The architecture is simulated with the cadence micro wind software. As shown in the above Table \hyperref[tab_0]{.}1. The proposed work of the MOS transistors with normal threshold voltage was used at critical path. It is observed that 4-bit Braun multiplier using proposed Work4 Power Delay Product 119 femito (10 -15 ), with Reference paper \hyperref[b10]{[11]}, it is observed that 46\% of power Delay Product has been reduced. \section[{II.}]{II.} \section[{Proposed Work}]{Proposed Work}( ) ( ) in in Sum A B C A B C = ? + ? (1) ( ) ( ) out in C A B C A B A = ? + ?\textbf{(2)}\par As shown in the above Table \hyperref[tab_0]{.}2. The proposed work of the MOS transistors with low threshold voltage was used at critical path. It is observed that 4-bit Braun multiplier using proposed Work2 we got Power Delay Product 111 femito (10 -15 ), but comparatively to the Reference paper \hyperref[b10]{[11]}, it is 51\% of power Delay Product has been reduced.\par As shown in the above Table \hyperref[tab_0]{.}3. The proposed work of the MOS transistors with high threshold voltage was used at critical path. It is observed that 4-bit Braun multiplier using proposed Work1 Power Delay Product 120 femito (10 -15 ), with Reference paper \hyperref[b10]{[11]}, it is observed that 47\% of power Delay Product has been reduced.\par As shown in the above Table \section[{Conclusion}]{Conclusion}\par The present paper demonstrated the improvement in parameters v/s, Area, power, and delay with reduction in number of transistors to implement Full adder circuits. The simulations were performed using 90nm Micro wind 3 CMOS layout CAD Tool In this paper power consumption \& Power Delay Product is calculated the results are optimized power consumption of 46\% and Power Delay Product is 56 \% still the performance of 4-Bit CMOS Braun Multiplier is improved by incorporating techniques which support reduced transistor implementations.\begin{figure}[htbp] \noindent\textbf{}\includegraphics[]{image-2.png} \caption{\label{fig_0}A}\end{figure} \begin{figure}[htbp] \noindent\textbf{12233445}\includegraphics[]{image-3.png} \caption{\label{fig_1}Fig. 1 :Fig. 2 : 2 Fig. 3 : 3 Fig. 4 : 4 Fig. 5 :}\end{figure} \begin{figure}[htbp] \noindent\textbf{6}\includegraphics[]{image-4.png} \caption{\label{fig_2}Fig. 6 :}\end{figure} \begin{figure}[htbp] \noindent\textbf{}\includegraphics[]{image-5.png} \caption{\label{fig_3}}\end{figure} \begin{figure}[htbp] \noindent\textbf{7}\includegraphics[]{image-6.png} \caption{\label{fig_4}Figure 7 :}\end{figure} \begin{figure}[htbp] \noindent\textbf{84}\includegraphics[]{image-7.png} \caption{\label{fig_5}Figure 8 : 4 -}\end{figure} \begin{figure}[htbp] \noindent\textbf{.} \par \begin{longtable}{P{0.44776785714285716\textwidth}P{0.11668526785714287\textwidth}P{0.07779017857142856\textwidth}P{0.099609375\textwidth}P{0.07114955357142856\textwidth}P{0.03699776785714286\textwidth}} 4-bit Multiplier\tabcellsep 60.055\tabcellsep 4.270\tabcellsep 256\tabcellsep 5534\tabcellsep \\ proposed\tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \\ work2\tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \\ 4-bit Multiplier\tabcellsep 25.594\tabcellsep 4.695\tabcellsep 120\tabcellsep 5516\tabcellsep \\ proposed\tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \\ work3\tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \\ 4-bit Multiplier\tabcellsep 74.600\tabcellsep 6.860\tabcellsep 511\tabcellsep 5660\tabcellsep \\ proposed\tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \\ work4\tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \\ 4-bit Multiplier\tabcellsep 24.524\tabcellsep 6.025\tabcellsep 147\tabcellsep 5752\tabcellsep \\ proposed\tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \\ work5\tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \\ \multicolumn{5}{l}{Proposed 4-bit Braun Multiplier Low V T (Low Threshold voltage) \& High V T (High Threshold voltage) Table.4 Power(µw) Delay(ns) Power Delay Product Area (µm 2 )}\tabcellsep \\ Multipliers Proposed\tabcellsep Power(µw)\tabcellsep delay(ns)\tabcellsep femito(10 -15 ) Power Delay\tabcellsep Area (µm 2 )\tabcellsep \\ Proposed 4x4 Multipliers 2011 IEEE paper 4-bit Multiplier proposed work1 4-bit Multiplier proposed work2 2011 IEEE 4-bit Reference Multipliers paper 4-bit Multiplier proposed work1 4-bit Multiplier proposed work2 4-bit Multiplier proposed 2011 IEEE paper 4-bit Multiplier proposed work1 4-bit Multiplier proposed work2 4-bit Multiplier work3 4-bit Multiplier proposed work4 4-bit Multiplier proposed work5 work5 proposed work3 4-bit Multiplier proposed work4 proposed 4-bit Multiplier\tabcellsep Power(µw) 45.686 30.702 25.992 45.686 54.302 30.089 28.404 45.686 24.448 26.743 64.600 25.063 27.444 28.321 29.235\tabcellsep delay(ns) 5.270 4.691 4.277 5.270 4.695 4.615 4.695 5.270 4.270 4.695 6.435 4.785 4.990 5.340 4.695\tabcellsep Power Delay Product femito(10 -15 ) 237 144 111 237 Product femito (10 -15 ) 254 138 133 237 104 125 415 119 136 151 137\tabcellsep Area (µm 2 ) 5610 5354 5654 5610 5712 5456 5910 5610 5524 5918 5706 5661 5700 5959 5736\tabcellsep Issue IX Version I of Researches in Engineering ( ) F Volume XIV\\ 4-bit Multiplier proposed work3 4-bit Multiplier proposed work4 4-bit Multiplier proposed work5\tabcellsep 26.194 28.475 29.586\tabcellsep 4.690 4.785 5.055\tabcellsep 122 136 149\tabcellsep 5504 5500 57.26\tabcellsep Global Journal\\ \tabcellsep \multicolumn{3}{l}{Braun Multiplier High V T (High Threshold voltage) Table.3}\tabcellsep \tabcellsep \\ Proposed\tabcellsep Power(µw)\tabcellsep delay(ns)\tabcellsep Power Delay\tabcellsep Area (µm 2 )\tabcellsep \\ 4-bit Multipliers\tabcellsep \tabcellsep \tabcellsep Product femito(10 -15 )\tabcellsep \tabcellsep \\ 2011 IEEE\tabcellsep 45.686\tabcellsep 5.270\tabcellsep 237\tabcellsep 5610\tabcellsep \\ paper\tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \\ 4-bit Multiplier\tabcellsep 26.553\tabcellsep 4.695\tabcellsep 124\tabcellsep 5530\tabcellsep \\ proposed\tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \\ work1\tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \end{longtable} \par \caption{\label{tab_0}Table . 1}\end{figure} \footnote{© 2014 Global Journals Inc. (US)} \backmatter \begin{bibitemlist}{1} \bibitem[Mutoh (1995)]{b8}\label{b8} ‘1-V Power Supply High-speed Digital Circuit Technology with Multi-threshold-Voltage CMOS’. S Mutoh . \textit{IEEE Journal of Solis-State Circuits} August 1995. 30 (8) p. . \bibitem[Liao et al. ()]{b0}\label{b0} ‘A carry-selectadder optimization technique for high-performance booth-encoded wallace-tree multipliers’. M J Liao , C F Su , C Y Chang , A C H Wu . \textit{IEEE International Symposium on Circuits and Systems ISCAS}, 2002. p. . \bibitem[Sung et al. ()]{b5}\label{b5} ‘A power aware 2-dimensional bypassing multiplier using cellbased design flow’. G N Sung , Y J Ciou , C C Wang . \textit{IEEE International Symposium on Circuits and Systems}, 2008. \bibitem[Anitha and Bagyaveereswaran (2011)]{b7}\label{b7} ‘Braun's Multiplier Implementation using FPGA with Bypassing Techniques’. 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