@incollection{,
	
					
					
					415A5CB82D8983B370DB802D16379C93
				,
	author={{DayadiLakshmaiah} and {CJITS,JANGON,WARNAGAL}},
	journal={{Global Journal of Researches in Engineering}},
	journal={{GJRE}}2249-45960975-586110.34257/gjre,
	address={Cambridge, United States},
	publisher={Global Journals Organisation}1491721
}

@incollection{b0,
	
	
		,
	title={{A carry-selectadder optimization technique for high-performance booth-encoded wallace-tree multipliers}}
		,
	author={{
			MJLiao
		} and {
			CFSu
		} and {
			CYChang
		} and {
			AC HWu
		}}
		
		
		
	
	
		,
	booktitle={{IEEE International Symposium on Circuits and Systems ISCAS}}
				
			,
	year={2002}
			
		
	

}

@incollection{b1,
	
	
		,
	title={{Multiplexer-based array 9}}
		,
	author={{
			KZPekmestzi
		}}
	
	
		,
	booktitle={{Digital Integrated Circuits}}
				,
	editor={
			JMRabaey
			AChandrakasan
			BNikolic
		}
		
			,
	publisher={Prentice Hall Publications}
			,
	year={2003}
		
	

}

@incollection{b2,
	
	
		,
	title={{Low power parallel multiplier with column bypassing}}
		,
	author={{
			MCWen
		} and {
			SJWang
		} and {
			YMLin
		}}
		
		
	
	
		,
	booktitle={{IEEE International Symposium on Circuits and Systems}}
				
			,
	year={2005}
		
	

}

@incollection{b3,
	
	
		,
	title={{Multiplier energy reduction through Bypassing of partial products}}
		,
	author={{
			JOhban
		} and {
			VGMoshnyaga
		} and {
			KInoue
		}}
		
		
	
	
		,
	booktitle={{IEEE Asia-Pacific Conference on Circuits and Systems}}
				
	

}

@incollection{b4,
	
	
		,
	title={{Low-power multiplier design with row and column bypassing}}
		,
	author={{
			JTYan
		} and {
			ZWChen
		}}
		
	
	
		,
	booktitle={{IEEE International SOC Conference}}
				
			,
	year={2009}
			
		
	

}

@incollection{b5,
	
	
		,
	title={{A power aware 2-dimensional bypassing multiplier using cellbased design flow}}
		,
	author={{
			GNSung
		} and {
			YJCiou
		} and {
			CCWang
		}}
		
		
	
	
		,
	booktitle={{IEEE International Symposium on Circuits and Systems}}
				
			,
	year={2008}
		
	

}

@incollection{b6,
	
	
		,
	title={{Hardware Implementation of Truncated Multipliers Using Spartan-3AN, Virtex-4 and Virtex-5 FPGA Devices}}
		,
	author={{
			HMuhammad
		} and {
			Rais
		}}
		
	
	
		,
	journal={{Am. J. Engg. & Applied Sci}}
		
			,
	year={2010}
		
	

}

@incollection{b7,
	
	
		,
	title={{Braun's Multiplier Implementation using FPGA with Bypassing Techniques}}
		,
	author={{
			RAnitha
		} and {
			VBagyaveereswaran
		}}
		
	
	
		,
	booktitle={{International Journal of VLSI Design and Communication Systems (VLSICS)}}
				
			,
	year={September, 2011}
			2
		
	

}

@incollection{b8,
	
	
		,
	title={{1-V Power Supply High-speed Digital Circuit Technology with Multi-threshold-Voltage CMOS}}
		,
	author={{
			SMutoh
		}}
	
	
		,
	journal={{IEEE Journal of Solis-State Circuits}}
		
			30
			8
			
			,
	year={August 1995}
		
	

}

@book{b9,
	
	
		,
	title={{Dr. k. Satya Prasad design of Low power 1 bit ALU, IJETS}}
		,
	author={{
			DLakshmaiah
		} and {
			DrM VSubramanyam
		}}
		
		
			,
	year={2014}
			6
		
	

}

@book{b10,
	
	
		,
	title={{Singh Design and analysis of low power 1-bit full adder cell}}
		,
	author={{
			DeepaSinha
		} and {
			TriptiSharma
		} and {
			KGSharma
		} and {
			ProfB P
		}}
		
		
		
		
			,
	year={2011}
			6
		
	

}