@incollection{,
	
					
					
					8176AD2124B7E3182993615A7F4F77F1
				,
	author={{MalothSanthoshi} and {Mrs. E PVanetha} and {P.Srikanth} and {Vardhaman College of Engineering}},
	journal={{Global Journal of Researches in Engineering}},
	journal={{GJRE}}2249-45960975-586110.34257/gjre,
	address={Cambridge, United States},
	publisher={Global Journals Organisation}149711
}

@book{b0,
	
	
		,
	title={{A Novel Architecture of LUT Design Optimization for DSP Application}}
		
	

}

@incollection{b1,
	
	
		,
	title={{Hardware Efficient Approach for Memoryless-Based Multiplication and Its Application to FIR Filter}}
		,
	author={{
			PREmail
		}}
		
	
	
		,
	journal={{Jianjun He Institute of Information Science and Engineering}}
		
		
			Central South University, Changsha, P.R. China Jiafeng XieInstitute of Information Science and Engineering, Central South University
		
	

}

@book{b2,
	
	
		,
	title={{Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool" re with INESC-ID, Lisbon 1000-029, Portugal (e-mail:levent,
	algos}}
		,
	author={{
			LAksoy
		} and {
			CLazzari
		}}
		
		
	
	,
	note={inesc id.pt; lazzari,
	algos. pt}

}

@book{b3,
	
	
		,
	title={{Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication Accumulation Shen-Fu Hsiao}}
		,
	editor={Jun-Hong Zhang Jian, and Ming-Chih Chen}
		
	

}

@incollection{b4,
	
	
		,
	title={{Optimization of area in digital FIR filters using gatelevel metrics}}
		,
	author={{
			LAksoy
		} and {
			ECosta
		} and {
			PFlores
		} and {
			JMonteiro
		}}
		
		
		
	
	
		,
	booktitle={{Proc. DAC}}
				DAC
		
			,
	year={2007}
			
		
	

}

@incollection{b5,
	
	
		,
	title={{Optimization of area in digit-serial multiple constant multiplications at gate-level}}
		,
	author={{
			LAksoy
		} and {
			CLazzari
		} and {
			ECosta
		} and {
			PFlores
		} and {
			JMonteiro
		}}
		
		
		
		
	
	
		,
	booktitle={{Proc. ISCAS}}
				ISCAS
		
			,
	year={2011}
			
		
	

}

@incollection{b6,
	
	
		,
	title={{Efficient shift-adds design of digit-serial multiple constant multiplications}}
		,
	author={{
			LAksoy
		} and {
			CLazzari
		} and {
			ECosta
		} and {
			PFlores
		} and {
			JMonteiro
		}}
		
		
		
		
	
	
		,
	booktitle={{Proc. Great Lakes Symp. VLSI}}
				Great Lakes Symp. VLSI
		
			,
	year={2011}
			
		
	

}

@incollection{b7,
	
	
		,
	title={{Exact and approximate algorithms for the optimization of area and delay in multiple constant multiplications}}
		,
	author={{
			LAksoy
		} and {
			ECosta
		} and {
			PFlores
		} and {
			JMonteiro
		}}
		
		
		
	
	
		,
	journal={{IEEE Trans. Comput.-Aided Design Integr. Circuits Syst}}
		
			27
			6
			
			,
	year={Jun. 2008}
		
	

}

@book{b8,
	
	
		,
	title={{Senior Member, IEEE Manuscript received}}
				
			,
	year={June 25. 2009. 2009. April 21. 2010}
		
		
			LUT Optimization for Memory-Based Computation Pramod Kumar Meher
		
	
	,
	note={revised November 14}

}

@book{b9,
	
	
		,
	title={{LUT Optimization Using Combined APC-OMS Technique For Memory-Based Computation Mrs}}
		,
	editor={R.RAMYA#1 Mrs.S.SUDHA IJCAES -V-III -SI -NCIC}
		
			,
	year={13 -AUG-2013}
		
	

}

@book{b10,
	
	
		,
	title={{Optimization of Area in Digit-Serial Multiple Constant Multiplications at Gate-Level the Portuguese Foundation for Science and Technology (FCT) research project PTDC/EIA-EIA}}
		
			,
	year={103532/2008}
		
	

}