# Introduction hree phase DC/AC Voltage Source Inverters (VSI's) are now used extensively in motor drives, active filters and unified power flow controllers in power systems and uninterrupted power supplies to generate controllable frequency and AC voltage magnitudes using various pulse-width modulation (PWM) strategies. Of the possible PWM methods, the carrier-based PWM is very popular due to its simplicity of implementation, defined harmonic waveform characteristics and low harmonic distortion. Two main implementation techniques exist for PWM: the direct digital method and the sine-triangle intersection scheme. In the traditional sine-triangle intersection PWM (SPWM) technique, three reference modulation signals are compared with a triangular carrier signal and the intersections define the switching instants of the controllable devices. PWM strategies are required for switching the devices in a VSI appropriately to generate variable voltage, variable frequency, 3-phase AC required for the variable speed induction motor drive. The performance of the drive strongly depends on the Pulse width Modulation (PWM) technique employed. At high power levels, the inverter distortion is quite high. Hence, PWM strategies for high-power drives must aim in reducing the inverter switching losses, harmonic distortion, subject to low switching frequencies of the inverter. This zero sequence waveform is used to alter the duty cycle of the inverter switches. Adding the same zero sequence waveform to each of the three reference phase voltages does not change the inverter output lineline voltage per carrier cycle average value; however, if the waveform is properly selected, one can achieve any of the followings: switching losses can be drastically reduced, the waveform quality may be improved, the linear modulation range can be extended, and common mode voltage of motor drives can also be drastically diminished. These potentials have been explored leading to investigations into and determination of various zero sequence waveforms, resulting in a large number of published carrier-based PWM methods. When the augmenting zero sequence waveform is continuous, the continuous PWM (CPWM) scheme is produced; however when the zero sequence signal is discontinuous with a potential for the modulator to have phase segments clamped either to the positive or negative rails, the scheme is called the discontinuous PWM (DPWM). The zero-voltage injection has been fully exploited but to different purposes: adding a zerovoltage sequence can serve not only to linearity extension, but also to reducing switching losses. In order to reduce switching losses the simplest method is not to switch: the idea was possible using zero-voltage sequences that saturate one of the modulation wave of the three phases. There are about six variations reported in the literature under the name Discontinuous Pulse Width Modulation (DPWM) viz., DPWM0, DPMW1, DPWM2, DPWM3, DPWMMAX and DPWMMIN. The basic idea behind all these variations are employing discontinuous modulating signal instead of basic sinusoidal signal while carrier remains the triangular function. DPWM modulation techniques have the advantage of eliminating one switching transition in each half carrier interval, which allows the switching frequency to increase by a nominal value of 3/2 accordingly for the same inverter losses. This may improve the harmonic performance of the inverter by virtue of the reduced The proposed carrier-based non-sinusoidal and discontinuous modulation schemes are experimentally implemented with an TMS320F2812 DSP Processor, intelligent power modules and used to modulate a threephase inverter feeding a three-phase induction machine. # Principle of Dpwm and its Variants a) 120 o Discontinuous Modulation In this type of modulation, each phase leg in turn is now continuously locked to the upper or lower DC rail (whichever is chosen) for one-third of the fundamental cycle (120°).DPWMMAX and DPWMMIN strategies come under this category. In DPWMMAX, each phase around the peak is locked to the upper DC rail for one-third of the fundamental cycle (120 o ) as shown in Figure 1(a) and hence the name. Each phase in DPWMMIN, is locked to the lower DC rail for one-third of the fundamental cycle (120 o ) as shown in the Figure 1(b).Due to the asymmetry in line-to-line voltage , it has been expected that the harmonic performance of 120°d iscontinuous PWM will be suboptimal compared to continuous modulation strategies. However, it has been identified that to maintain the same effective phase leg switching frequency as for continuous modulation, the space vector calculation frequency (i.e. twice the carrier frequency) should be increased by approximately 50%, since each phase leg only switches during two-thirds of each fundamental cycle. It is trade-off between these two effects that offers potential advantages for 120°d iscontinuous PWM under some modulation conditions. A further limitation with this strategy is that one device of each phase leg is always turned off during its 120°u nmodulated region, while the other device is always conducting. Hence conduction losses are not shared equally across the two devices in each phase leg. Another improved discontinuous modulation strategy in which each phase leg is now unmodulated for only 60° at a time (alternately switched to the upper or to the lower DC rail).It has the particular benefit that the line-to-line switched voltages are symmetrical. This type of discontinuous switching pattern is termed as DPWM1 and centers the non-switching periods for each phase leg symmetrically around the positive and negative peaks of its fundamental reference voltage. This is the best position for resistive load, since the peaks of the line currents follow the peaks of the fundamental voltages. Therefore each phase leg does not switch just when the current is at its maximum value, and this obviously minimizes switching losses. The modulating waveform for DPWM1 is as shown in the Figure 2 It is viable to place each 60 ? non-switching period anywhere within the 120 ? region where the appropriate phase leg reference voltage is the maximum/minimum of the three-phase set. For example, the 60 ? "clamp to + dc V "non switching period for phase leg 'a' can be placed anywhere in the region This freedom allows alternative 60 ? discontinuous PWM strategies to be considered which minimize the switching losses for loads which are not unity power factor. For a lagging power factor (pf) load, it is clearly preferable to retard the non-switching period by up to a maximum of 30 ? (pf of 0.866 lag), depending on the load current power factor. This is the discontinuous modulation strategy DPWM2 and its modulating waveform is as shown in figure 2(ii).For a leading power factor load, the non switching period can be advanced by up to 30 ? (pf of 0.866 lead).This is discontinuous modulation strategy DPWM0 and its modulating waveform is shown in Figure 3 In DPWM, the modulating signal is discontinuous in nature comprised of different functions for each section of time reference. There are six functions which are substituted in various sections of time reference. The differences among the DPWM schemes are just interchange of these sections. Table 1, 2, 3, 4, 5 and 6 details the expressions for the modulation waves of various DPWM variants for one complete cycle. In all the cases, it has been understood that the phase leg reference segments are in fact sections of the required line-to-line voltage, referenced to the phase leg which is clamped to either the upper or the lower DC rail. The variation of M does not have any effect in the saturation region of the modulating wave. # Performance Evaluation Parameters that is taken in consideration for performance evaluation of the proposed DPWM methods namely Total Harmonic Distortion (THD) is defined in by equations ( 1), (1) Where V n represents n th order harmonic component and V 1 represent fundamental output phase voltages. The lowest order harmonic contents (upto 25 th order) are considered for calculation of THD. The resulting THD are shown in Figure 4. Their measured %THDs is compared (Table - It is seen from that at low modulation index the THD of DPWMMAX is lowest compared to all other schemes and DPWM1 has highest THD. Since the DPWMMAX may not be employed for implementation purposes, thus the next best scheme is DPWM2. At high modulation index the value of THD is smaller compared to the value at lower modulation index, which implies that the output voltage is very near to the sinusoidal. DPWM1 has the lowest THD and DPWM0 and DPWM3 has highest THD at high modulation index. iv. # Experimental Results The proposed DPWM techniques has been implemented in real time using Texas Instrument TMS320F2812 DSP Processor, intelligent power modules and was programmed through the software Vissim. The DSP board is integrated interfacing communication board. The PC is connected to the DSP board through printer parallel port. The DSP board is connected through cable to the Inverter intelligent power modules. Current sensors are used for feedback purposes. The code is run using Code Composer studio CCS 3.2V, and the .out file thus created is then converted to the ASCII file which is loaded to the DSP for further processing. The complete experimental set up is illustrated in Figure 5 # Conclusions The paper present PWM technique termed as Discontinuous PWM for voltage source inverter. This 1![Figure 1 : Modulating waveform for phase 'a' (a)DPWMMAX (b) DPWMMIN However, this limitation can be avoided by clamping to alternate DC buses every half cycle (i.e. cycle between the DPWMIN and the DPWMMAX strategies). b) 60 o and 120 o Discontinuous Modulation](image-2.png "Figure 1 :") ![(a).](image-3.png "") 2![Figure 2 : Modulating waveform for phase 'a' (a)DPWM1 (a) DPWM2](image-4.png "Figure 2 :") 3![the 'a' phase reference voltage is more positive than the other two phase reference voltages during this period. Similarly, the "clamp todc V " nonswitching period for phase leg 'a' can be placed anywhere in the region 2? 4? 3 , since this is the region where the 'a' phase fundamental voltage is more negative than the other two-phase reference voltages.](image-5.png "3 â??"") ![(a). It should be noted however, that incorporating this advance/retard of the Global Journal of Researches in Engineering ( ) F Volume XIV Issue VIII Version I 2 Year 2014 non switching period reintroduces asymmetry into the line-to-line voltage as shown in the figure 3(b). The final variation is to clamp the phase legs to the opposite DC rails in each 60 ? segment as shown in the figure. This strategy is referred as 30 ? discontinuous modulation-DPWM3, since it requires the clamping phase leg to change every 30 ? as shown in figure 3(ii).](image-6.png "") 3![Figure 3 : Modulating waveform for phase 'a' (a)DPWM0 (b) DPWM3](image-7.png "Figure 3 :") ![+1-3 * M*cos( ?+ ) 6 5? +1+ 3 * M*cos(?+ )](image-8.png "?") 6113420146![* M*cos(?+ ) M*sin(?) Global Journal of Researches in Engineering ( ) F Volume XIV Issue VIII Version I Year Composite modulating function-DPWM3iii.](image-9.png "6 - 1 - 1 - 3 * 4 2014 Table 6 :") ![7).](image-10.png "") 4![Figure 4 : Harmonic spectra (% of fundamental) , (a) for DPWMMAX ; (b) for DPMIN ; (c) for DPWM 1; (d) for DPWM 2 ; (e) for DPWM 3 and (f) for DPWM 0](image-11.png "Figure 4 :") ![(a) and (b).](image-12.png "") 5![Figure 5 : Experimental set-up (a) TMS320F2812 DSP board and Intelligent Power Module (b) Induction Motor with Load setup](image-13.png "Figure 5 :") 6![Figure 6 : Line voltage and Line Current of, (a) for DPWMMAX; (b) for DPMIN; (c) for DPWM 1; (d) for DPWM 2; (e) for DPWM 3 and (f) for DPWM 0 Illustrative experimental results are given in Figures 6 (a), (b), (c), (d), (e), (f) and (g) showing voltage and current waveforms when a loaded induction machine is fed with a voltage source inverter under various types of generalized discontinuous modulation.](image-14.png "Figure 6 :") ![proposed method of PWM offers a reduction in overall number of switching and consequently switching losses.. The analysis is done on the basis of THD in Journals Inc. (US) output phase voltages. It can be concluded that the DPWMMAX provide lowest THD for low modulation index. However, this method is not recommended for practical implementation as this may shorten the life of inverter. DPWM2 offers the next best result and thus it may be used for implementation. At high modulationGlobal Journal of Researches in Engineering ( ) F Volume XIV Issue VIII Version I 10 Year 2014](image-15.png "") 1 2Alpha (degree)Phase APhase BPhase C0-30 0+1? +1-3 * M*cos( ?+ ) 65? +1+ 3 * M*cos( ?+ ) 6 3 4 5Alpha (degree)Phase APhase BPhase C0-60 0+1? +1-3 * M*cos(?+ ) 65? +1+ 3 * M*cos(?+ ) 6 © 2014 Global Journals Inc. (US) ## v. index DPWM1 is recommended for use. The viability of the proposed schemes is validated using simulation and experimental result * New sinusoidal pulsewidth modulated inverter SRBowes Proc. Inst. Elect. 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