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\title{Digital Frequency Synthesis using Multi-Phase NCO for Dielectric Characterization of Materials on Xilinx Zynq FPGA}
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             \author[1]{M.Sandhya  Rani}

             \affil[1]{  INTELLECTUAL ENGINEERING COLLEGE}

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\date{\small \em Received: 9 December 2013 Accepted: 2 January 2014 Published: 15 January 2014}

\maketitle


\begin{abstract}
        


Precise measurement of dielectric characteristics of materials is becoming necessity in several engineering applications. The dielectric constant measurement over wide frequency range for emerging applications such as PCB manufacturing, agriculture, environmental and food processing industries has several challenges. With the advancement in digital VLSI and Field Programmable Gate Array (FPGA) based processing the digital techniques for estimating the dielectric constant are feasible. In this context the digital based frequency generation techniques over wide frequency are discussed in this paper. The multi phase Numerically Controlled Oscillator (NCO) based technique for generating high frequency signals are experimented in this paper. The efficient implementation of NCO for Xilinx Zynq family FPGA, XC7Z020 device is simulated here. The realized multi phase NCO is observed to be occupying only 15% of resources and operating at 250MHz to result efficient synthesis of sine wave with sampling frequency of 1GHz. The design issues related to digital carrier generation on FPGAs, while driving high frequency Digital to Analog Converters (DACs) are discussed and simulation results are presented here.

\end{abstract}


\keywords{dielectric measurement, digital phase, FPGA, multi phase NCO, Zynq SOC FPGA.}

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\let\tabcellsep& 	 	 		 
\section[{I. Introduction}]{I. Introduction}\par
he dielectric properties measurement is necessary because it can provide the electrical or magnetic characteristics of the materials, which proved useful in many research and development fields \hyperref[b0]{[1]} \hyperref[b8]{[10]}. The present work is aimed to evolve digital multi phase technique for generating high frequency sinusoid signal using FPGAs, which becomes useful in precise dielectric characterization of materials.\par
The work presented in this paper is part of ongoing research \hyperref[b0]{[1]}  \hyperref[b7]{[9]} aimed for precise characterization of printed circuit board (PCB) at high frequencies (order of Hundreds of MHz). This paper discusses the multi phase NCO based technique for generating high frequency sine wave, which is required in this context.\par
Measurement of dielectric properties requires measurements of the complex relative permittivity (? r ) and complex relative permeability (? r ) of the materials \hyperref[b0]{[1]}. The complex dielectric permittivity consists of real and imaginary parts. The real part of the complex permittivity is referred as dielectric constant and it is a measure of the amount of energy from an external electrical field stored in the material. The imaginary part is indicative of the amount of energy that gets dissipated in material when it is subjected to electric field \hyperref[b0]{[1]}. The imaginary part is zero for lossless materials. The term loss tangent is defined as given in \hyperref[b0]{(1)} which indicates the dissipative nature of material with respect to the energy storage nature \hyperref[b9]{[11]}.tan ? = ?? ?? ?? ?? ?? ? = 1 Q\par
The vector diagram for loss tangent is shown in Fig. \hyperref[fig_0]{1}. Loss tangent is also referred as quality factor (Q). The circuit equivalent of real and imaginary parts of permittivity can be well derived from capacitor action \hyperref[b0]{[1]}.  The voltage across capacitor can be given as equation (  {\ref 4}) whose phase term can be computed as in equation \hyperref[b3]{(5)}.?? ?? = ?? 1+???? ?? ?? ?? ?? ? ?? ?? = ? tan ?1 ? 1 ???? ?? ?? ?? ? ?? 
\section[{?}]{?}\par
The phase shift between V and V C is a function of dielectric constant for all remaining being constant values. The dielectric constant measurement through digital techniques is possible, if the signal with angular frequency ?? can be generated digitally and the phase shift between and V and V C is measured accurately \hyperref[b1]{[2]}. The FPGA based techniques for sinusoid generation using NCO is an established area and being widely used in communication applications. However the maximum synthesizable signal with NCO is limited to F clk /2, where F clk is the clock at which the NCO runs.\par
To enable dielectric Constant measurement up to high frequencies it is required that the FPGA based circuit should be able to generate the signal up to the desired frequency. Above in equation (  {\ref 4}) ?= 2?f and f=frequency at which dielectric constants are measured. In conventional implementation of NCO the realizable frequency by NCO is given in equation \hyperref[b4]{(6)} Where F clk = clock frequency at which NCO is running N= size of bit width phase registered ?p = input phase increment word Since F clk and N are fixed for a particular implementation, the input phase increment word (?p) describes the frequency of the output sine wave. The first register in the Fig. \hyperref[fig_3]{3}. latches the frequency controlled word on the clock edge and the accumulator realized by added and register continuously accumulates input frequency word and generates the phase. This phase accumulator generates the digital phase, which is input to sine lookup table. The sine lookup table generates the digital amplitude samples of sine waves  {\ref [3]}. The digital samples of sine wave need to be supplied to DAC chip which generates corresponding analog sine wave. The analog sine wave after passing through low pass filter will be suitable for dielectric constant measurement. The low pass filter removes the spurious harmonic signals which are present in DAC output.
\begin{quote}
.\end{quote}
\par
The present day available RF DAC \hyperref[b4]{[6]}[13] enables high frequency sine wave up to 1 GHz provided the digital part is capable of generating suitable samples.\par
With the present day available FPGA technology the max achievable frequency F clock is up to 300 MHz only which means the maximum F o that can be generated is 150MHz only, Where as the necessity of dielectric constant measurement of PCB materials is up to few Mega Hertz to Giga Hertz frequencies.\par
This becomes limitation of digital based carrier generation for high frequency dielectric constant characterization of materials. The present paper implementation of multi phase NCO based architecture enables digital generation of sine wave samples [3], which can be used while interfacing with RF DACs \hyperref[b4]{[6]} \hyperref[b11]{[13]} by which the concept of digital dielectric constant can be extended up to Hundreds of Mega Hertz to Giga Hertz frequency level. The remaining part of the paper is organized into three sections. Section 2 explains the high level architecture of multiphase digital NCO. Section 3 explains the simulation and synthesis results including the resource utilization summary for ZED board. The last section provides conclusion and future scope of the work. 
\section[{II. High Level Architecture}]{II. High Level Architecture}\par
This section presents high level architecture of proposed multiphase NCO based sine wave generation \hyperref[b2]{[4]}. Multiphase NCO technique in principal uses the inverse concept of distributed arithmetic. The distributed arithmetic (DA) principle is an area optimization technique usually implemented in FPGAs and Application Specific Integrated Circuits (ASICs), where certain hardware is made to run at high frequency than the actual throughput required. Utilizing same resource for multiple operations in different clock cycles allows achieving area optimization. For e.g. in a digital logic the requirement is to multiply numbers at 10MHz rate. The FPGA logic employing DA technique runs at 100MHz. The multiplier input is multiplexed and output is demultiplexed to perform 10 multiplications by using single unit.\par
In multiphase NCO the concept is reverse implementation of resource sharing. In the present Implementation on the ZED board \hyperref[b10]{[12]} it is aimed to generate sine wave 400 MHz by achieving sampling frequency of 1GHz.\par
In this implementation 4 NCO modules are made to run as parallel blocks which shall maintain phase offsets corresponding to their sample position. The sine wave generation \hyperref[b2]{[4]} is illustrated in fig.  {\ref 4}. 
\section[{Scheme of multiphase NCO for high frequency digital}]{Scheme of multiphase NCO for high frequency digital}\par
The effective sampling rate achieved is denoted as F s and is given at \hyperref[b5]{(7)}.F s = 4 X F clk\textbf{(7)}\par
Fig.  {\ref 5} : Set of 4 NCOs generating samples at F s The effective sampling rate achieved is denoted as F s and is given at \hyperref[b5]{(7)}. The NCOs are fed with phase shifts such that the samples generated by all NCOs form successive samples in sine wave at higher sampling rate F s . The figure  {\ref 5} has the illustration of the same.\par
The initial phase shifts can be computed by a series of adders, where at each stage Î?"? is added \hyperref[b4]{[6]}. Fig.  {\ref 5} : Samples generated by each NCO in the sin wave at F s As the uniformly sampled phase results in spurious values at the multiples of sampling frequency, the phase dithering is implemented. In the phase dithering a pseudo noise binary signal (PN) is used to produce a random number. This random numbers are added to phase accumulator output, before applying to the address inputs of SIN and COS look up tables. 
\section[{III. Simulation and Synthesis Results}]{III. Simulation and Synthesis Results}\par
The simulation results for the implemented logic are given in this section. The figure \hyperref[b4]{(6)} The simulation results showing the generated sine waves on all four channels are shown in figure \hyperref[fig_5]{7}. The resultant signal when applied to multi channel DAC is simulated by a mod 4 counter based interleaving logic, placing samples from each channel as illustrated in fig.  {\ref 5}. The last waveform in Fig. \hyperref[fig_5]{7}, RF\textunderscore DAC\textunderscore SIG shows the generated sine wave with F s sampling rate. The logic is synthesized using Xilinx's ISE 14.6 tool and the area and speed analysis are carried out. The area utilization summary and maximum clock estimate of the implemented digital logic \hyperref[b5]{[7]} For ZED board (XC7Z020) FPGA \hyperref[b3]{[5]}, are given at fig.  {\ref 8}.  \begin{figure}[htbp]
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 			\footnote{© 2014 Global Journals Inc. (US)} 			\footnote{© 2014 Global Journals Inc. (US) (3) (4)(5) (6)Digital Frequency Synthesis using Multi-Phase NCO for Dielectric Characterization of Materials on Xilinx Zynq FPGA} 		 		\backmatter  			 
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\end{document}
