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\title{ASIC Design, Implementation and Exploration on High Speed Parallel Multiplier}
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             \author[1]{Y. Narasimha  Rao}

             \affil[1]{  GITAM University}

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\date{\small \em Received: 16 December 2013 Accepted: 4 January 2014 Published: 15 January 2014}

\maketitle


\begin{abstract}
        


Designing multiplier is always a challenging and interesting job, in order to satisfy user needs as per demand.Vedic multiplier is prominent system for faster result and optimized circuit design. In any digital system the throughput and power consumption decides the performance. The present work mainly concentrated on Vedic multiplier power consumption and throughput. In much faster computing and parallel processing architectures, pipeline motivates for higher throughput. This is motivated to incorporate pipeline in the present work to enhance the performance of the Vedic multiplier. In the present paper, area and power consumption is also taken into consideration along with throughput. These parameters are compared for different fast adders such as RCA, CSLA, LFA, BKA, KGA in Vedic multiplier. The Vedic multipliers are designed and analysed using Cadense RTL Compiler v08.10.

\end{abstract}


\keywords{throughput, power consumption, area, pipeline, fast adders, vedic multiplier.}

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\let\tabcellsep& 	 	 		 
\section[{Introduction}]{Introduction}\par
ast adders and multiplications are ever needed in many DSP systems Multiplication operations also form the basis for other complex operations such as convolution, Discrete Fourier Transform, Fast Fourier Transforms, etc. With ever increasing need for faster clock frequency it becomes imperative to have faster arithmetic unit \hyperref[b0]{[1]}.Another important area on which is required to concentrate is the power dissipation and speed. There is always an interrelation between power dissipated and speed of operation ever known to all. Vedic multiplier is famous for fast operation and less power consumption with respect to bit size. Vedic multiplier is adopted from ancient Indian mathematics which is stated in Atharva Veda. His Holiness Jagadguru Shankaracharya Bharati Krishna Teerthaji Maharaja (1884-1960) comprised andgave mathematical explanation while discussingit for various applications. Swamiji constructed 16 formulae and 16 sub formulae after extensive research in Atharva Veda  {\ref [2] [3]}.A general block diagram of Vedic Multiplier is shown in figure  {\ref 1}. 
\section[{Figure 1 : Block diagram of Vedic Multiplier}]{Figure 1 : Block diagram of Vedic Multiplier}\par
There are many adders effectively working in many different types of multipliers. A time, area, and power consumption is studies in previous work \hyperref[b3]{[4]} \hyperref[b4]{[5]}, which are the base work for the present paper. The Carry Look-Ahead Adder (CLA) requires large area and consumes high power with respect to the bit size. So there is a Speed limitation with respect to bit size \hyperref[b5]{[6]}. Unlike CLA the carry-select adder (CSA) increases its are a requirements to enhance its speed performance. In CSA irrespective of arrival of carry-in, the sum will arrive at output. So it will take less time than other methods to calculate the sum \hyperref[b6]{[7]}[8]. In the proposed work Parallel Prefix Adders (PPA) are selected because addition is done quicker than traditional adders. The large fan-out in PPA can be eliminated by increasing the number of levels of cells and buffers \hyperref[b4]{[5]}. The Koggstone Adder (KSA) is most widely used adder for high performance. It has very low fan-out which makes it performance high \hyperref[b7]{[9]}. The Brent-Kung adder (BKA) requires less area and minimum interconnecting wires than Kogge-Stone adder \hyperref[b7]{[9]}[10]. The Ladner-Fischer Adder (LFA) adder requires less area when compared with KSA, but has large fan-out \hyperref[b7]{[9]}[10]. 
\section[{II.}]{II.} 
\section[{Motivation}]{Motivation}\par
In the previous paper few parameters are measured and compared for Vedic Multiplier with different fast adders. Based on these results it is observed that LFA is selected with less area and less power consumption \hyperref[b4]{[5]}. Hence the next work is extended with implementation of Pipelined Vedic Multiplier (PVM) with LFA. So In the previous work it is tested and observed that a good throughput is achieved in PVM when compared with Traditional Vedic Multiplier F Global Journal of Researches in Engineering ( ) (TVM) \hyperref[b3]{[4]}. It is also analysed that as the pipeline is incorporated in traditional circuit, the cell area increased little more when compared with traditional Vedic multiplier. The increase in cell area also leads more power consumption. These analyses done with Ladner Fischer adder (LFA)under Parallel Prefix Adder (PPA) structure \hyperref[b3]{[4]}. Although the circuit complexity increased in the PVM \hyperref[b3]{[4]} it is observed that it has relatively less power consumption and better throughput when compared with other existing techniques. This motivates us to measure all the parameters of PVM with all adders. This may lead to a new significant of work. In the present paper the PVM is also tested with various other adders for identifying better results and to find flaws with other adders. This work will be more interesting for future researchers. 
\section[{III.}]{III.} 
\section[{Proposed Work}]{Proposed Work}\par
In the present work a new architecture is proposed for Vedic Multiplier. Although this method is proposed in my past paper \hyperref[b3]{[4]}, but in the present paper pipeline is applied to all different types of fast adders as case study and makes us flexible to select an adder according to the requirement. It is observed some exciting results with each adder. Each adder is idiosyncratic for a specific application. In the proposed work two 8-bit data A (0:7) and B (0:7) is taken for multiplication.\par
In the present method pipeline stages are integrated at individual stages of PPA as shown in figure  {\ref 1[4]}. Figure \hyperref[fig_0]{2} is showing a comprised block diagram of Pipelined Vedic Multiplier (PVM). After adding these pipeline stages the circuit area increases and hence the power consumption also increases when compared with TVM. But this varies from one adder to another adder. So the pipeline technology is applied to all adders and tested to choose best adder with high performance. As each adder is peculiar for a parameter we can consider any adder as per the requirement, and we can simply neglect other adders as they are important in some other area. In figure \hyperref[fig_0]{2} latches are place in between input, multiplier and adders. Initially all input are entered into 4bit Vedic multiplier through first stage of latches. The partial product generated at first stage will enter into next stage latches and the second partial product will be generated and passed through at third stage latches and final product will be produced at last adder circuit. The adder circuit implies all adders such as RCA, CSLA, LFA, BKA, and KGA.\par
IV. 
\section[{Results}]{Results}\par
The circuit is designed and analysed using Cadense RTL Compiler v08.10.The circuit is tested on different adders like RCA, CSLA, LFA, BKA, and KGA with and without pipeline technology. Table \hyperref[tab_0]{1} is showing measured parameters such as Area, Throughput and Power Consumption in TVM and PVM with different adders. The area represented in terms of number of gates, Throughput measured in Nanoseconds (ns) and power consumption indicated in milliwatts (mw). Figure  {\ref 3} and Figure  {\ref 4} are showing relative work between TVM and PVM. Figure  {\ref 5} is showing RTL schematic of a Pipelined Vedic Multiplier. Figure  {\ref 6}.1a to 6.1c is showing simulation results of Brent-Kung adder (BKA) showing cell area, delay and power consumption respectively.     \begin{figure}[htbp]
\noindent\textbf{2}\includegraphics[]{image-2.png}
\caption{\label{fig_0}Figure 2 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{7}\includegraphics[]{image-3.png}
\caption{\label{fig_1}Figure 7 .}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-4.png}
\caption{\label{fig_2}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{9}\includegraphics[]{image-5.png}
\caption{\label{fig_3}Figure 9 .}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{3469}\includegraphics[]{image-6.png}
\caption{\label{fig_4}Figure 3 :Figure 4 :Figure 6 .Figure 9 .}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-7.png}
\caption{\label{figure7}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-8.png}
\caption{\label{figure8}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{1} \par 
\begin{longtable}{P{0.85\textwidth}}
Year 2014\\
60\\
XIV Issue VI Version I\\
) F Volume\\
(\\
Global Journal of Researches in Engineering\end{longtable} \par
 
\caption{\label{tab_0}Table 1 :}\end{figure}
 			\footnote{© 2014 Global Journals Inc. (US)} 			\footnote{© 2014 Global Journals Inc. (US) ASIC Design, Implementation and Exploration on High Speed Parallel Multiplier} 		 		\backmatter   			  			  			 
\subsection[{Conclusion}]{Conclusion}\par
The Traditional Vedic Multiplier consumes less power as it circuit complexity is simple. But the data speed is slow in TVM. In pipeline Vedic Multiplier while first partial product is generating the second input (next 8-bit data) can be fetched into the multiplier. A High throughput is observed in Pipelined Vedic multiplier when compared with Traditional Vedic Multiplier. In parallel prefix adders a constant throughput is achieved. But KGA could be best adder as it has less number of gates and consuming less power than other parallel prefix adders. Overall the performance of the pipelined Vedic Multiplier is high when compared with Regular Vedic Multiplier. 
\subsection[{Biography}]{Biography}\par
Mr. Y. Narasimha Rao, working as Assistant professor, in the department of Information technology, GITAM University, Visakhapatnam, has more than 10 years academic experience. He has completed his Masters degree from Acharya Nagarjuna University. He has published couple of research papers in reputed international journals and conferences. Presently he is			 			  				\begin{bibitemlist}{1}
\bibitem[Hoe ()]{b5}\label{b5} 	 		‘Design and characterization of parallel prefix adders using FPGAs’.  		 			D H K Hoe 		.  	 	 		\textit{IEEE, 43rd Southeastern Symposium on System},  				2011.  	 
\bibitem[Kumar (2012)]{b2}\label{b2} 	 		‘Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques’.  		 			G 		,  		 			Ganesh Kumar 		.  	 	 		\textit{International Journal of Scientific and Research Publications}  		March 2012. 2  (3)  p. .  	 
\bibitem[Narasimharao ()]{b3}\label{b3} 	 		‘Design of high speed vedic multiplier with pipeline technology’.  		 			Y Narasimharao 		.  	 	 		\textit{JATIT}  		2014. 67.  	 
\bibitem[Desiree (2013)]{b6}\label{b6} 	 		‘Fast and Area Efficient RSA Cryptosystem Design Using Modified Montgomery Multiplication for FPGA Applications’.  		 			J V Desiree 		.  	 	 		\textit{IJSER, vol4 no7},  				July 2013.  	 
\bibitem[Saligram]{b0}\label{b0} 	 		‘Optimized Reversible Vedic Multipliers for High Speed Low Power Operations’.  		 			Rakshith Saligram 		.  	 	 		\textit{Proceedings of 2013 IEEE Conference on Information and Communication Technologies (ICT 2013)},  				 (2013 IEEE Conference on Information and Communication Technologies (ICT 2013))  		p. .  	 
\bibitem[Jyoshna ()]{b7}\label{b7} 	 		‘Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic’.  		 			G Jyoshna 		.  	 	 		\textit{UACEE International journal of Advances in Electronics Engineering}  		2011. 1  (1) .  	 
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\bibitem[Narasimharao (2014)]{b4}\label{b4} 	 		‘Studies and Performance Evaluation of Vedic Multiplier using Fast Adders’.  		 			Y Narasimharao 		.  	 	 		\textit{IJCET}  		Jun 2014. 4 p. .  	 
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