@incollection{,
	
					
					
					79E08B39B97FFD7F66C860E86BB80988
				,
	author={{Y. NarasimhaRao} and {GITAM University}},
	journal={{Global Journal of Researches in Engineering}},
	journal={{GJRE}}2249-45960975-586110.34257/gjre,
	address={Cambridge, United States},
	publisher={Global Journals Organisation}1466369
}

@incollection{b0,
	
	
		,
	title={{Optimized Reversible Vedic Multipliers for High Speed Low Power Operations}}
		,
	author={{
			RakshithSaligram
		}}
	
	
		,
	booktitle={{Proceedings of 2013 IEEE Conference on Information and Communication Technologies (ICT 2013)}}
				2013 IEEE Conference on Information and Communication Technologies (ICT 2013)
		
			
		
	

}

@incollection{b1,
	
	
		,
	title={{Vedic Mathematics or Sixteen Simple Sutras From The Vedas}}
		,
	author={{
			JagadguruSwami
		} and {
			SriBharath
		} and {
			KrsnaTirathji
		}}
		
		
	
	
		,
	booktitle={{Motilal Banarsidas}}
				Varanasi (India
		
			,
	year={1986}
		
	

}

@incollection{b2,
	
	
		,
	title={{Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques}}
		,
	author={{
			G
		} and {
			GaneshKumar
		}}
		
	
	
		,
	journal={{International Journal of Scientific and Research Publications}}
		
			2
			3
			
			,
	year={March 2012}
		
	

}

@incollection{b3,
	
	
		,
	title={{Design of high speed vedic multiplier with pipeline technology}}
		,
	author={{
			YNarasimharao
		}}
	
	
		,
	journal={{JATIT}}
		
			67
			,
	year={2014}
		
	

}

@incollection{b4,
	
	
		,
	title={{Studies and Performance Evaluation of Vedic Multiplier using Fast Adders}}
		,
	author={{
			YNarasimharao
		}}
	
	
		,
	journal={{IJCET}}
		
			4
			
			,
	year={Jun 2014}
		
	

}

@incollection{b5,
	
	
		,
	title={{Design and characterization of parallel prefix adders using FPGAs}}
		,
	author={{
			DH KHoe
		}}
	
	
		,
	booktitle={{IEEE, 43rd Southeastern Symposium on System}}
				
			,
	year={2011}
		
	

}

@incollection{b6,
	
	
		,
	title={{Fast and Area Efficient RSA Cryptosystem Design Using Modified Montgomery Multiplication for FPGA Applications}}
		,
	author={{
			JVDesiree
		}}
	
	
		,
	booktitle={{IJSER, vol4 no7}}
				
			,
	year={July 2013}
		
	

}

@incollection{b7,
	
	
		,
	title={{Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic}}
		,
	author={{
			GJyoshna
		}}
	
	
		,
	journal={{UACEE International journal of Advances in Electronics Engineering}}
		
			1
			1
			,
	year={2011}
		
	

}

@incollection{b8,
	
	
		,
	title={{Reconfigurable VLSI architecture for FFT computation}}
		,
	author={{
			KSreenath
		}}
	
	
		,
	journal={{IJSER}}
		
			3
			6
			,
	year={june 2012}
		
	

}