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\title{Design of a Novel Low-Power SRAM Column}
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\begin{document}

             \author[1]{Sunil Ojha  }

             \affil[1]{  Amity University}

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\date{\small \em Received: 15 December 2013 Accepted: 3 January 2014 Published: 15 January 2014}

\maketitle


\begin{abstract}
        


A novel SRAM column was designed. SRAM column includes SRAM cell, column select circuit, precharging circuit, and sense amplifier. The transmission gates are used for word line access in place of pass transistors which rectify the voltage drop problem; also there is an NMOS switch at the bottom of the cell which restricts the short circuit current flowing through the cell during operation. Using the standard process parameters of the PTM 7nm transistor model the SRAM column was simulated by HSPICE. The simulation results indicate the proper logic operation of the column and also it shows the low power operation.

\end{abstract}


\keywords{SRAM column, storage cell, precharging circuit, NMOS switch, sense amplifier.}

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\let\tabcellsep& 	 	 		 
\section[{Introduction}]{Introduction}\par
tatic random access memory (SRAM) is widely used in present day logic LSIs. SRAM memory cell array normally occupies around 40\% of the chip area and hence affects the operating speed, power, supply voltage, and chip size. Therefore, a good design of SRAM cell and SRAM cell array is essential. This paper present a novel SRAM column architecture using standard 7nm process technology provided by the predictive technology model (PTM) \hyperref[b8]{[9]}.Various kinds of SRAM memory cell have been proposed, developed, and used. To resolve the problem of switching capacitances at the word line clocked transmission gate adiabatic SRAM has been designed \hyperref[b0]{[1]}, this topology uses the bootstrapped NMOS transistors and CMOS latch structure to recover the charge of large switching capacitances on word-line, write bit line, and sense amplified lines and so on. Since this circuit uses clocked transmission gate logic as well as sampling of the input signals so it may be slower comparatively, also it has floating nodes for some period of time which may not be desired for the memory array, this design also uses sub array selection signal with some delays which is again not desirable; all these issues has been taken care for the presented design. Now the variations in the threshold voltage (Vt) for the transistors of the cell may create some undesired effects which are again resolved by controlling the memory cell-power line (MCPL) and word-line voltage \hyperref[b1]{[2]},this design provide low current operation with negligible area penalty; in this design the word line voltage is changed stepwise which may effect in slower operation of the memory array; furthermore in these circuits, the memory cell power line voltage is almost equal to Vdd, which is not very effective for resolving the Vt variation problem. The MCPL cannot be decreased to ground because the data of the unselected word line (WL) vanish if the MCPL set to ground, here the data vanishes because the MCPL is shared with different loads. Also in the conventional six transistors (6-T) SRAM cell \hyperref[b5]{[6]} there will be voltage drop problem at the word line access which increases the overall power dissipation of the cell; also there may be a short circuit current flowing through the circuit. All these problems have been taken care for this novel design. 
\section[{II.}]{II.} 
\section[{Proposed Sram Column}]{Proposed Sram Column}\par
Fig. \hyperref[fig_0]{1} shows the design of a proposed SRAM column. It includes precharging circuit (mo \& m1) from where the precharged voltage is generated and this equalizes the bit and bit-bar lines with equal potential, storage cell (m2 -m7) is used to store the data [either 0 or 1] in the memory cell, sense amplifier (m8 -m12) is used during reading operation of the required data from the memory array and column select circuit (m13 \& m14) used to select the corresponding column from the memory array. Working of this design can be understood in the following mode viz. i) Read, ii) Write.\par
For the first case when a read control signal is given to the column, it first selects the respective column, then the precharging circuit is activated and the voltage Vp is transferred to the bit and bit-bar lines which makes both the lines at equal potential. After that the word lines (WL and WLB) are activated which enable the transfer of stored values on the memory cell (either 0 or 1) to the bit lines resulting in one of the bit line go high and the other bit lines go low. Finally the sense amplifier is enabled which senses the potential difference between bit and bit-bar lines and transmits the signals to the bi-directional input-output data lines.\par
For write operation a write signal is applied to select the respective column without activating the precharging circuit. The data (either 0 or 1) to be entered is supplied by bi-directional input-output data lines to the bit lines. The word line is then activated to store the required information into the cell. Note that for efficient read or write operation the transistor sizing should be appropriate otherwise it may leads to wrong data read or write. For the standby operation word line (WL) voltage is not applied to the cell hence the stored information remains latched and the inverters connected back to back reinforce each other and maintain the required data into the cell.\par
The proposed SRAM column includes two transmission gates (TG-1 and TG-2) in place of pass transistors for word line access transistors, the use of pass transistors as word line shows the voltage drop problem for the cell but in case of transmission gates there is negligible voltage drop. Also as there is a static current flow through the cell during memory cell operation (especially when writing the data to the cell), so to restrict the short circuit current the NMOS switch (m6) is used at the bottom of the cell which turns on during memory cell operation and shows high resistance to the current flow. The proposed SRAM column was simulated using HSPICE simulator. The design parameters (or process parameters) for the column was taken from PTM and the technology used here is standard 7nm. The Vdd was 0.8 V. The trapezoidal clock pulse was used for the word line access. The simulation results for reading and writing of the SRAM column are shown in fig.  {\ref 2}   
\section[{Simulation Results}]{Simulation Results}\par
Fig.  {\ref 2} shows the simulated waveforms of proposed SRAM column during read cycle; furthermore fig.  {\ref 2 (a)} shows the waveform of precharge signal (Vp and pre) which is transferred in equalized manner to the bit and bit-bar (BL and BLB) lines of the column. Also fig.  {\ref 2 (b)} shows the waveform of word line (WL and WLB) which is trapezoidal in nature, after the arrival of word line signal the stored data will be transferred to the bit lines which makes one bit line to go high and other to go low depending on the data stored, and then after column select (c\textunderscore sel) and sense enable (sen) signals the values at the bit and bit-bar lines will be read out and can be seen at the bidirectional and data-bar lines.\par
Global Journal of Researches in Engineering ( ) F Volume XIV Issue V Version  The values of power dissipation during various operations of the proposed SRAM column are listed in table-1 as shown below.  
\section[{Conclusion}]{Conclusion}\par
In summary, a new SRAM column was designed by using standard 7nm process models from PTM. In the design transmission gates are used in place of pass transistors to rectify the voltage drop problem, an additional NMOS switch is also used at the bottom of the cell instead connecting the cell directly to the ground this helps in reducing the static current flow through the cell during memory operation especially during writing the data to the memory cell. Trapezoidal wave pulses are used at the word line access signal which helps in reducing the power of the memory cell. Finally, by observing the output files generated by HSPICE it was concluded that the proposed SRAM column consumes low power and functioning correctly.\begin{figure}[htbp]
\noindent\textbf{1}\includegraphics[]{image-2.png}
\caption{\label{fig_0}Figure 1 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{22}\includegraphics[]{image-3.png}
\caption{\label{fig_1}Figure 2 Figure 2 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{33}\includegraphics[]{image-4.png}
\caption{\label{fig_2}Figure 3 Figure 3 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-5.png}
\caption{\label{figure5}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-6.png}
\caption{\label{figure6}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-7.png}
\caption{\label{figure7}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{1} \par 
\begin{longtable}{P{0.5283783783783783\textwidth}P{0.3216216216216216\textwidth}}
During Read Operation\tabcellsep 1.45 * 10 -4 W\\
During Write Operation\tabcellsep 4.70 * 10 -5 W\\
IV.\tabcellsep \end{longtable} \par
 
\caption{\label{tab_0}Table 1 Proposed SRAM Column Average Power Consumed}\end{figure}
 			\footnote{© 2014 Global Journals Inc. (US)} 			\footnote{© 2014 Global Journals Inc. (US) Design of a Novel Low-Power SRAM Column} 			\footnote{Design of a Novel Low-Power SRAM Column} 		 		\backmatter  			  				\begin{bibitemlist}{1}
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\bibitem[ HSPICE User Guide Simulation and Analysis]{b9}\label{b9} 	 		\textit{},  		 Version: A-2008.03.  	 	 		\textit{HSPICE User Guide Simulation and Analysis}  		 	 
\bibitem[Nakata (2009)]{b1}\label{b1} 	 		‘Adiabatic SRAM with a Large Margin of VT Variation by Controlling the Cell-Power-Line and Word-Line Voltage’.  		 			S Nakata 		.  	 	 		\textit{IEEE International Symposium on Circuits and Systems},  				May-2009. p. .  	 
\bibitem[Qazi (2011)]{b3}\label{b3} 	 		‘Challenges and Directions for Low-Voltage SRAM’.  		 			Masood Qazi 		.  	 	 		\textit{IEEE Council on Electronic Design and Automation}  		Feb. 2011. p. .  	 
\bibitem[Neil et al. ()]{b7}\label{b7} 	 		\textit{CMOS VLSI Design: A Circuits and Systems Perspective},  		 			H E Neil 		,  		 			David Money Weste 		,  		 			Harris 		.  		2011. Addison Wesley.  	 
\bibitem[Yu (2006)]{b0}\label{b0} 	 		‘Design of Adiabatic SRAM Based on CTGAL Circuit’.  		 			Jun-Jun Yu 		.  	 	 		\textit{IEEE International Conference on Solid-State and Integrated Circuit Technology},  				Oct-2006. p. .  	 
\bibitem[Rabaey et al. ()]{b5}\label{b5} 	 		\textit{Digital integrated circuits: a design perspective},  		 			Jan M Rabaey 		,  		 			Anantha P Chandrakasan 		,  		 			Borivoje Nikolic 		.  		2003. Pearson Education.  	 
\bibitem[Kang and Leblebici]{b6}\label{b6} 	 		 			Sung-Mo Kang 		,  		 			Yusuf Leblebici 		.  		\textit{CMOS Digital Integrated Circuits: Analysis and Design},  				Tata McGraw-Hill Education.  	 
\bibitem[Athes (1994)]{b4}\label{b4} 	 		‘Low-power Digital systems based on adiabatic-switching principles’.  		 			W C Athes 		.  	 	 		\textit{IEEE Transaction on VLSI Systems}  		Dec. 1994.  (2)  p. .  	 
\bibitem[Zhang (2008)]{b2}\label{b2} 	 		‘Low-Power SRAMs in Nanoscale CMOS Technologies’.  		 			Kevin Zhang 		.  	 	 		\textit{IEEE Transactions on Electron Devices}  		Jan. 2008. p. .  	 
\end{bibitemlist}
 			 		 	 
\end{document}
