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\def\makelabel##1{\upshape ##1}}% } {\end{list}\end{raggedright}} \newenvironment{specHead}[2]% {\vspace{20pt}\hrule\vspace{10pt}% \phantomsection\label{#1}\markright{#2}% \pdfbookmark[2]{#2}{#1}% \hspace{-0.75in}{\bfseries\fontsize{16pt}{18pt}\selectfont#2}% }{} \def\TheFullDate{2014 2014-01-15 (revised: 23 Year 2014 15 January 2014)} \def\TheID{\makeatother } \def\TheDate{2014 2014-01-15} \title{Low Power Conditional Sum Adder using Modified Ripple Carry Adder} \author{}\makeatletter \makeatletter \newcommand*{\cleartoleftpage}{% \clearpage \if@twoside \ifodd\c@page \hbox{}\newpage \if@twocolumn \hbox{}\newpage \fi \fi \fi } \makeatother \makeatletter \thispagestyle{empty} \markright{\@title}\markboth{\@title}{\@author} \renewcommand\small{\@setfontsize\small{9pt}{11pt}\abovedisplayskip 8.5\p@ plus3\p@ minus4\p@ \belowdisplayskip \abovedisplayskip \abovedisplayshortskip \z@ plus2\p@ \belowdisplayshortskip 4\p@ plus2\p@ minus2\p@ \def\@listi{\leftmargin\leftmargini \topsep 2\p@ plus1\p@ minus1\p@ \parsep 2\p@ plus\p@ minus\p@ \itemsep 1pt} } \makeatother \fvset{frame=single,numberblanklines=false,xleftmargin=5mm,xrightmargin=5mm} \fancyhf{} \setlength{\headheight}{14pt} \fancyhead[LE]{\bfseries\leftmark} \fancyhead[RO]{\bfseries\rightmark} \fancyfoot[RO]{} \fancyfoot[CO]{\thepage} \fancyfoot[LO]{\TheID} \fancyfoot[LE]{} \fancyfoot[CE]{\thepage} \fancyfoot[RE]{\TheID} \hypersetup{citebordercolor=0.75 0.75 0.75,linkbordercolor=0.75 0.75 0.75,urlbordercolor=0.75 0.75 0.75,bookmarksnumbered=true} \fancypagestyle{plain}{\fancyhead{}\renewcommand{\headrulewidth}{0pt}} \date{} \usepackage{authblk} \providecommand{\keywords}[1] { \footnotesize \textbf{\textit{Index terms---}} #1 } \usepackage{graphicx,xcolor} \definecolor{GJBlue}{HTML}{273B81} \definecolor{GJLightBlue}{HTML}{0A9DD9} \definecolor{GJMediumGrey}{HTML}{6D6E70} \definecolor{GJLightGrey}{HTML}{929497} \renewenvironment{abstract}{% \setlength{\parindent}{0pt}\raggedright \textcolor{GJMediumGrey}{\rule{\textwidth}{2pt}} \vskip16pt \textcolor{GJBlue}{\large\bfseries\abstractname\space} }{% \vskip8pt \textcolor{GJMediumGrey}{\rule{\textwidth}{2pt}} \vskip16pt } \usepackage[absolute,overlay]{textpos} \makeatother \usepackage{lineno} \linenumbers \begin{document} \author[1]{Anjana R.} \author[2]{Anjana R.} \author[3]{Vicky Kanoji} \affil[1]{ Laxmi institute of Technology} \renewcommand\Authands{ and } \date{\small \em Received: 15 December 2013 Accepted: 5 January 2014 Published: 15 January 2014} \maketitle \begin{abstract} Carry select adder (CSeLA) is mainly used to alleviate the propagation delay caused by carry bit and upon which sum bit is generated. It produces n+1 sum from n bits. In this Paper, a simple Gate level implementation of regular Carry Select Adder is compared with our proposed work. Based on the comparison made in terms of power, delay and area, it is found that there is considerable reduction in area and power with delay overhead. Both regular and proposed methods are modeled using 180nm CMOS technology. From the results obtained, it is clear that proposed CSeLA is better than regular CSeLA. \end{abstract} \keywords{CMOS, delay efficient, CSeLA, low power, Propagation delay.} \begin{textblock*}{18cm}(1cm,1cm) % {block width} (coords) \textcolor{GJBlue}{\LARGE Global Journals \LaTeX\ JournalKaleidoscope\texttrademark} \end{textblock*} \begin{textblock*}{18cm}(1.4cm,1.5cm) % {block width} (coords) \textcolor{GJBlue}{\footnotesize \\ Artificial Intelligence formulated this projection for compatibility purposes from the original article published at Global Journals. However, this technology is currently in beta. \emph{Therefore, kindly ignore odd layouts, missed formulae, text, tables, or figures.}} \end{textblock*} \let\tabcellsep& \section[{INTRODUCTION}]{INTRODUCTION}\par esigning power efficient, high performance adder is one of the major concerns as far as VLSI Sub system is considered. Speed is usually limited due carry propagation bit of an adder. The sum of final bit is generated by the carry propagation from the previous bit to next stage. The CSeLA consists of two multiplexed ripple carry adder and performs operation in parallel with carry Cin=0 and Cin=1, then final sum is selected through multiplexer (mux). Due to multiplexed RCA, there is considerable increase in area, which reveals that there is scope for reduction in area \hyperref[b1]{[2]}.\par The main idea behind this work is to compare regular carry select adder with modified carry select adder. The modified carry select adder uses Boolean function based RCA along with modified XOR gate. The main advantage of this modified RCA comes with reduced gate count than the n-bit Full adder circuit.\par This paper is organized as follows. Section II deals with the delay and area measurement of conventional full adder. Section III explains the Boolean function based RCA design. Section IV shows the comparison between proposed methods with regular CSeLA. Section V shows the power and delay evaluation of regular CSeLA and modified CSeLA. The implementation method and results obtained are analyzed in Section VI. The work is finally concluded in Section VII.\par Author ?: Research Scholar, Deeksha Integrated, Bharathiar University, India. e-mail: anjana.lit@lvs.co.in Author ?: UG Student, Laxmi Institute of Tech, Sarigam, Gujarat, India. e-mail: vickykanoji@gmail.com Author ?: Department of Electronics Engineering, MANIT, Bhopal, India. e-mail: asomkumar@gmail.com II. \section[{DELAY AND AREA EVALUATION OF CONVENTIONAL ADDER}]{DELAY AND AREA EVALUATION OF CONVENTIONAL ADDER}\par The XOR gate is implemented using conventional AOI logic. The delay and area is found from this AOI logic, with the assumption that each gate having delay equal to one and the gate with the longest path contribute critical path delay. The total number of gate in AOI logic contributes to total area of logic block. Based on this method, 2:1 Mux, full adder, half adder, XOR are evaluated. The main idea is to use modified RCA instead of RCA with Cin=0 to reduce area and power consumption of regular CSeLA. The AOI implementation of full adder requires 14 gates, while the modified full adder CSeLA has two ripple carry adder with Cin=0 and Cin=1 and multiplexer to choose data one among them. One of two RCA is replaced with Boolean function (BF), which has reduced number of gate count. From the truth table of full adder its evident that sum is obtained from D ? The group 2 has two bit RCA, which comprises 1 FA and 1 HA with Cin=0 and other RCA with Cin=1 is replaced with modified BEC -1. \section[{Delay and area evaluation of CSeLA}]{Delay and area evaluation of CSeLA}\par ? Based on the delay and area analysis listed in Table {\ref I}, the total number of gate count for group 2 is ? Propagation delay of proposed carry select adder is given as, T Proposed = T s + (N-1) T mux + T sum = 3ns\par ? Area and delay is computed in same way as that of group 2 and listed in Table \hyperref[tab_0]{1}.\par V. \section[{Experimental Results}]{Experimental Results}\par The proposed work is designed using DSCH simulator and synthesized using 180nm technology. The synthesized verilognetlist is imported to Microwind and automatic layout is generated. From Microwind, power, area and delay is found by choosing different technology.\par Table \hyperref[tab_1]{2} shows the simulation results of both regular and modified CSeLA in terms of delay, power and area. Each individual cell in the design contributes the total cell area. Total power consumption is the sum of leakage power, switching power and static power. Area, power, delay, power delay product (PDP) is shown in fig. in terms of percentage reduction. The total power reduction for 8-b, 16-b, 32-b are 9.3 \%, 23.1\%, 9.7\% respectively. Similarly Percentage reduction in area is shown in fig. There is delay overhead of 14.9\%, 12.1\%, 6.18\% respectively. \section[{Conclusion}]{Conclusion}\par A modified approach for carry select adder is proposed in this paper to reduce power and delay compared to conventional CSLA. The modified structure of RCA and BEC provides the scope for further area reduction and power for 90nm technology. From the experimental results it is clear that there is 9.3 \%, 23.1\%, 9.7\% reduction in power and 10.5 \%, 24.9\%, 18.3\% reduction in area with 14.9\%, 12.1\%, 6.18\% delay overhead. The modified Carry Save Adder is thus area and power efficient.\begin{figure}[htbp] \noindent\textbf{1}\includegraphics[]{image-2.png} \caption{\label{fig_0}Figure 1 :}\end{figure} \begin{figure}[htbp] \noindent\textbf{3}\includegraphics[]{image-3.png} \caption{\label{fig_1}Figure 3 :}\end{figure} \begin{figure}[htbp] \noindent\textbf{456}\includegraphics[]{image-4.png} \caption{\label{fig_2}Figure 4 :Figure 5 :Figure 6 :}\end{figure} \begin{figure}[htbp] \noindent\textbf{7}\includegraphics[]{image-5.png} \caption{\label{fig_3}Figure 7 :}\end{figure} \begin{figure}[htbp] \noindent\textbf{}\includegraphics[]{image-6.png} \caption{\label{fig_4}}\end{figure} \begin{figure}[htbp] \noindent\textbf{11}\includegraphics[]{image-7.png} \caption{\label{fig_5}Figure 11 :}\end{figure} \begin{figure}[htbp] \noindent\textbf{1} \par \begin{longtable}{P{0.27019867549668874\textwidth}P{0.07880794701986756\textwidth}P{0.07880794701986756\textwidth}P{0.42218543046357615\textwidth}} 1-Bit Adder\tabcellsep Delay\tabcellsep Area\tabcellsep Issue V Version I\\ Full adder Half adder 2:1 MUX XOR AND\tabcellsep 6 3 3 3 1\tabcellsep 13 6 4 5 1\tabcellsep ( ) F Volume XIV\\ \tabcellsep \tabcellsep \tabcellsep of Researches in Engineering\\ \tabcellsep \tabcellsep \tabcellsep Global Journal\end{longtable} \par \caption{\label{tab_0}Table 1 :}\end{figure} \begin{figure}[htbp] \noindent\textbf{2} \par \begin{longtable}{P{0.09554263565891473\textwidth}P{0.312984496124031\textwidth}P{0.112015503875969\textwidth}P{0.10872093023255815\textwidth}P{0.10872093023255815\textwidth}P{0.112015503875969\textwidth}} Word Size\tabcellsep Adder\tabcellsep Power (mW)\tabcellsep Area(um 2 )\tabcellsep Delay(ns)\tabcellsep PDP(pW)\\ 8-Bit\tabcellsep Conventional CSLA\tabcellsep 0.32\tabcellsep 941\tabcellsep 1.61\tabcellsep 0.515\\ \tabcellsep Modified CSLA\tabcellsep 0.29\tabcellsep 842\tabcellsep 1.85\tabcellsep 0.3885\\ 16-Bit\tabcellsep Conventional CSLA\tabcellsep 0.69\tabcellsep 2435\tabcellsep 2.62\tabcellsep 1.80\\ \tabcellsep Modified CSLA\tabcellsep 0.53\tabcellsep 1829\tabcellsep 2.94\tabcellsep 1.55\\ 32-Bit\tabcellsep Conventional CSLA\tabcellsep 0.92\tabcellsep 4683\tabcellsep 4.93\tabcellsep 4.53\\ \tabcellsep Modified CSLA\tabcellsep 0.83\tabcellsep 3826\tabcellsep 5.13\tabcellsep 4.25\\ VI.\tabcellsep \tabcellsep \tabcellsep \tabcellsep \tabcellsep \end{longtable} \par \caption{\label{tab_1}Table 2 :}\end{figure} \footnote{© 2014 Global Journals Inc. (US)} \footnote{© 2014 Global Journals Inc. (US) Low Power Conditional Sum Adder Using Modified Ripple Carry Adder} \backmatter \subsection[{This page is intentionally left blank}]{This page is intentionally left blank} \begin{bibitemlist}{1} \bibitem[Bedrij ()]{b0}\label{b0} \textit{}, O J Bedrij . \textit{Carry-Select Adder, IRE Trans. Electron. Comput} 1962. p. . \bibitem[Kim and Kim (2001)]{b3}\label{b3} ‘64-Bit Carry-Select Adder With Reduced Area’. Y Kim , L.-S Kim . \textit{Electron. Lett} May 2001. 37 (10) p. . \bibitem[He et al. ()]{b5}\label{b5} ‘An Area Efficient 64-Bit Square Root Carry-Select Adder For Lowpower Applications’. Y He , C H Chang , J Gu . \textit{Proc. IEEE Int. Symp. Circuits Syst}, (IEEE Int. Symp. Circuits Syst) 2005. 4 p. . \bibitem[Ramkumar et al. ()]{b1}\label{b1} ‘ASIC Implementation Of Modified Faster Carry Save Adder’. B Ramkumar , H M Kittur , P M Kannan . \textit{Eur. J. Sci. Res} 2010. 42 (1) p. . \bibitem[Ceiang and Hsiao]{b2}\label{b2} ‘Carry-Select Adder Using Single Ripple Carry Adder’. T Y Ceiang , M J Hsiao . \textit{Electron. Lett} \bibitem[Rabaey ()]{b4}\label{b4} \textit{Digtal Integrated Circuits-A Design Perspective}, J M Rabaey . 2001. Upper Saddle River, NJ: Prentice-Hall. \bibitem[Ramkumar et al. (2012)]{b6}\label{b6} ‘Low-Power And Area-Efficient Carry Select Adder’. B Ramkumar , M Harish , Kittur . \textit{Global Journal of Researches in Engineering} February 2012. 20 (2) . (IEEE transaction on VLSI Systems) \end{bibitemlist} \end{document}