# Introduction raphene is a flat monolayer of sp 2 carbon atoms tightly packed into a two-dimensional (2D) honeycomb lattice including a linear energy dispersion relation [1]. Graphene offers many of the advantages such as high carrier mobilities up to 10×2 5 cm 2 V -1 s -1 in substrate supported devices and high saturation velocity [2] [6]. The novel electronic properties of graphene lead to intense research into possible applications of this material in nano scale devices such as dual gate graphene MOSFETs. There have been studies on designing and fabrication of dual gate graphene MOSFETs. However, the progress in designing and fabricating of G-MOSFETs is at initial stage. In order to fabricate high performance G-MOSFETs, understanding of detailed device modeling and performance evaluations is urgently required. The recent works have been concentrated mostly on the DC characteristics of large area graphene MOSFETs using different approaches. However, there have no significant works on AC characteristics although graphene is predicted to highly attracted material for nano-scale devices. # II. # Device Model A dual gated graphene MOSFET is considered for our work shown in Fig. 1. Graphene grown on metal and transferred to a SiO 2 covered Si wafer is used as the channel of the MOSFET. The length and width of the graphene channel are 5 µm and 1 m respectively. Here, HfO 2 (k=9) is used as top-gate oxide and SiO 2 (k=3.9) is used as back-gate oxide [5], [7]. The goal of this work is to model the highfrequency characteristics of these devices. This will be done by calculating the elements of the small-signal equivalent circuit. Before we can deal with these elements we need to know how to calculate the channel charge, since this is essential in order to determine the gate-source and gate-drain capacitances. In general the channel charge Q ch can he calculated by subtracting the amount of electrons from the amount of holes and multiplying the result by the elementary charge. This can be written as [09]. (01) To obtain Q ch , a simple numerical integration is performed using a trapezoidal approximation. The x dependence of the local hole and electron sheet densities can be translated into a dependence on the local voltage V(x). By using this equation It is important to distinguish between p, n and in the formula above. If we neglect the minority charge carriers, p(V(x))-n(V(x)) is equal to can be expressed as: ? ? ? L ch dx x n x p qW Q )) ( ( ) ( x V v I x V qW x dV (05) The integral to determine Qch is solved numerically. We have used the MATLAB simulation. Note that to calculate channel charge as well as small signal parameters the internal voltages have to be used The high-frequency behavior of the transistor can be modeled with a small-signal equivalent circuit [10] as shown in Figure2. The intrinsic transistor is described by the transconductance g m , the drain conductance gds, the gate-source capacitance C gs , and the gate-drain capacitance C gd . Thereby the whole behavior of the device is described by these four elements: g m , g ds C gs and C gd . The reason why this is possible is the following. The high-frequency AC signal is thought to be superimposed onto a DC signal, which defines the DC operating point. If the amplitude of the AC signal is small, the nonlinear transistor characteristics can be linearized around the DC operating point. Thus all elements of Fig. 2 The intrinsic transconductance, gm, is related to the internal small-signal gate source and drain-source voltages, VGSi and VDSi, whereas the terminal transconductance, gmt, is related to the applied gatesource and drain-source voltages, VGS and VDS [10]. # III. Transconductance Calculation The transconductance calculation is very important to know the radio-frequency characteristics of a graphene MOSFET. The transconductance is defined as the variation in the drain current caused by a small variation in the drain current caused by a small variation in the gate voltage. They are two types: intrinsic transconductance and drain-conductance. ? ? ? ? int 0 ) ( ) ( ))] ( ( )) ( ( [ ds V ch x dV x dV dx x V n x V p qW Q ) ( ) )) ( ( )) ( ( ( )] ( )) ( ( [ int 0 x dV x V v I x V qW x nV x V Q sat d V ch real ds ? ? ? ? ? ? ? ? ? real ? real ? q top ox top ox q back ox top gs top gs q top ox top ox q top ox top gs top gs C C C C C V x V V C C C C C V x V V x V n x V p 2 1 2 1 ) ) ( ( 2 1 2 1 ) ) ( ( )) ( ( )) ( ( 0 , 0 , ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const V # Intrinsic Capacitance Calculation The intrinsic capacitance is very necessary to calculate the cut-off frequency and other radiofrequency behaviour of a graphene MOSFET. The mobile channel charge depends on the top-gate voltage V gs-top-int , the back-gate voltage V gs-back-int and drain-source voltage V ds- The gate-drain conductance C gd is defined as the variation in the channel charge Q ch caused by a small variation in the drain-source voltage V ds-int with a fixed value of top-gate voltage V gs-top-int . (12) (13) The gate-drain capacitance due to the fixed value of top-gate voltage (C gd-top ) and the gate-drain capacitance due to the fixed value of back-gate voltage (C gd-back ) can be evaluated using Eqn.12 and Eqn.13 also. V. # Intrinsic Gain Calculation Finally, we show an example of projection of the intrinsic gain as a figure of merit commonly used in RF/analog applications. In small signal amplifiers, for instance, the transistor is operated in the ON-state and small RF signals that are to be amplified are superimposed onto the DC gate-source voltage [41]. Instead, what is needed to push the limits of many analog/RF figures of merit, for instance the cut-off frequency or the intrinsic gain, is an operation region where high trans conductance together with a small output conductance is accomplished. Next, we will give an example on how to use our current-voltage DC model to project an important figure-of-merit (FOM) used in RF/analog applications, namely the intrinsic gain (G). as the ratio of the transconductance to the drainconductance expressed as: Intrinsic top-gate gain, (14) The top-gate gain ( ) is very important in RF/analog applications as well as cut-off frequency. # b) Intrinsic Back-Gate Gain, Gback The intrinsic back-gate gain , which is defined as the ratio of the trans conductance ( ) to the drain-conductance ( ) expressed as: Intrinsic back-gate gain, (15) VI. VII. # Results and Discussion # Conclusion In this paper, the AC characteristics of a dual gated Graphene MOSFET are studied using analytical approach. The drain transconductance of the device is computed. We have simulated the top and back gate gain as a function of drain to source voltage. The resulting high intrinsic top ate ain 73 which is promising. 1![Figure 1 : Cross section of the modeled graphene MOSFET [8] a) Channel Charge Calculation](image-2.png "Figure 1 :") ![[09]. (02) The overall net charge can be expressed using G Global Journal of Researches in Engineering ( ) F Volume XIV Issue IV Version I 21 Year 2014 © 2014 Global Journals Inc. (US)](image-3.png "") ![Rahman ? , Ashish Kumar Roy ? , Md. Shamim Sarker ? & Md. Tajul Islam ?](image-4.png "") ![are explained in the following as mentioned [09].](image-5.png "") )) ( ) ( ( )) ( ( © 2014 Global Journals Inc. (US) * The rise of graphene AKGeim KSNovoselov Nature Materials 6 2007 * Graphene transistors FSchwierz Nature Nanotechnology 5 2010 * Two-dimensional gas of mass less Dirac fermions in graphene KSNovoselov AKGeim Nature 438 2005 * Detection of individual gas molecules adsorbed on graphene FSchedin AKGeim Nature Materials 6 2007 * Current saturation in zero-bandgap, top-gated graphene field-effect transistors IMeric MYHan AFYoung Nature Nanotechnology 3 2008 * Ultrahigh electron mobility in suspended graphene KIBolotina KJSikesb ZJianga MKlimac GFudenberga JHonec PKima HLStormer Solid State Communications 2008 146 * AKGeim Graphene: Status and Prospects 2009 324 * DC Characteristics of Dual Gated Large Area Graphene MOSFET Md *Tawabur Rahman AshishKumarRoy HossainMd MdAbu Reza Bhuiyan AshrafulGIslam Bhuiyan 2013 Khulna, Bangladesh Int. Conference on EICT * Modeling of graphene metal-oxide-semiconductor field-effect transistors with gapless large-area graphene channels SAThiele JASchaefer FSchwierz J. Appl. Phys 107 94505 2010 * Graphene transistors FSchwierz Global Journal of Researches in Engineering 5 2010 Nature Nanotechnology