# Introduction

uantum technology has gradually applied in various fields [1,2]. Quantum-dot cellular automata are projected as a promising nanotechnology for future ICs [3,4]. A QCA is an array of structures known as quantum-dots. Computing with QCA is achieved by the tunneling of individual electrons among the quantum-dots inside individual electrons among the quantum-dots inside a cell and the classical columbic interaction among them.

Author ? ? ? ?: Department of Information and Communication Technology, Mawlana Bhashani Science and Technology University, Tangail, Bangladesh. e-mail: bahar_mitdu@yahoo.com A quantum cell can be viewed as a set of four charge containers or dots positioned at the corners of a square, as shown in Fig. 1. It contains two extra mobile electrons. The electrons can quantum mechanically tunnel between dots but cannot come out from the cell and are forced to settle at the corner positions due to coulomb interaction. Thus, there exist two equivalent energetically minimal arrangements for the electrons in a QCA cell (Figure 1), a QCA cell and its binary Logic are shown, the energetically position of the diagonal electrons identifies the binary logic 0 or 1. This phenomenon is useful in nanotechnology which affects high resolution fast electronic circuits. The QCA cells themselves comprise the interconnecting wires as described in [4]. An example of a QCA wire is shown in Figure 2. In this example, a value of 1 is transmitted along the wire. Only a slight polarization in a cell is required to fully polarize its neighbor. The direction for the flow of information through a gate or a wire is controlled by a four stage clocking system described in [4] which raises and lowers barriers between the cells. Described in [3] were other logic gates formed by restricting the polarity of one input to the 3-input majority gate to be a constant value. Figure 3 illustrates a 2-input AND gate and a 2-input OR gate formed in this manner. By replacing input c with a cell having a fixed  


# Proposed Circuit and Presentation a) BCD-to-EXCESS-3 code converter

A conversion circuit must be inserted between the two systems if each uses different codes for the same information. Thus, a code converter is a circuit that makes the two systems compatible even though each uses a different binary code. To convert from binary code A to binary code B, the input lines must supply the bit combination of elements as specified by code A and the output lines must generated the corresponding bit combination of code B. A combinational circuit performs this transformation by means of logic gate. The design procedure of code converters will be illustrated by means of a specific example of conversion from the BCD to the excess-3 code. The bit combinations for the BCD and excess-3 code [5] listed in Table 1. Since each code uses four bits to represent a decimal digit, there must be four input variables and four output variables. Let us designate the four input binary variables by the symbols A,B,C and D and the four output variables by the W,X,Y and Z .The truth table relating the input and output variables is shown in Table 2. The bit combinations for the inputs and their corresponding outputs are obtain directly from Table 1. We note that four binary variables may have 16bit combinations, only 10 of which are listed in the truth table. The six bit combinations not listed for the input variables are don't-care combinations. Since they will never occur, we are liberty to assign to the output variables either a 1 or a 0, whichever gives a similar circuit. The manipulation of BCD-to-excess code converter, shown below, illustrates the flexibility obtain with multiple-output systems when implemented with three or more levels of gates.  


# Z= D' Y= CD+(C+D)' Z= B'(C+D) + B(C+D)' W= A + B(C+D)
Input BCD Output Excess-3-code A B C D W X Y Z 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 1 1 0 0 0 0 1 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 0 0 0 1 0 1 1 1 0 0 1 1 1 0 0 b) BCD-to-EXCESS-3 code converter gate in QCA
The block diagram of QCA is the BCD-toexcess-3 code converter gate shown in Fig. 5. The BCDto-excess-3 code converter gate has four inputs and four outputs asshown in figure 5. Uses eight majority voter (MV) gate and two NOT gate to design BCD-toexcess-3 code converter in QCA as shown in Figure 5.The fundamental logic gate for QCA is the BCD-toexcess-3 code converter gate shown in Figure 6 that is composed of two hundred (200) cells with total area of 0.06 ?m2. Four of these, representing the inputs to the cell, are labeled A, B, C and D. using the terminology of [3]. The center cell is the "device cell" that performs the calculation for three input majority voter gates in QCA. The remaining cell, labeled out, provides the output. The circuit shown in Figure 6  


# Methods

First of all, the logic behind any proposed circuit is deduced and then the circuit diagram is drawn at gate level. The gate level circuit is converted to QCA layout using majority gates, inverters, etc. as described in the above sections and then these designs are simulated in QCA Designer which is the product of an ongoing research effort by the Walus Group at the University of British Columbia to create a design and simulation tool for QCA. The designer tool allows the designer to layout a QCA design and simulates it quickly. QCA Designer has provided a new platform for developers; results from simulations, using this tool, have been published by many international groups [6][7][8][9][10][11]. Results obtained by this tool are then compared to theoretical values to verify the correctness of the circuit.

IV.


# Simulation Result and Discussion

The circuit was functionally simulated using the QCA Designer.  We can find the Output value of W, X, Y, Z is two level such as low and high when the various input digits of A,B,C,D . We look into the every output values of W, X, Y, Z are translating the input data successfully. Based on the mentioned reversible logic gate BCD-to-excess-3 code converter gate numeral logical circuit design method, we also construct BCD-to-excess-3 code converter gate by QCA. The sizes of layouts are measured on the basis of size of QCA cells. The All designs are carefully clocked and were functionally verified using QCADesigner; a layout and simulation tool for QCA. Finally, in Table 3, designs are compared according to number of cells, area, and delay. Table 3 : Result analysis of proposed BCD-to-excess-3 code converter gate in QCA V.


# Conclusion

This paper present a BCD-to-excess-3 code converter gate based on QCA does logic gates .This QCA circuit design provide a new functional paradigm for information encoding. In addition, QCA binary logic functions and the associated new nano-technology will provide high-speed computing, high-density applications. It is believed that QCA will become a more practical ways to create a faster and denser circuit
1![Figure 1 : A QCA cell and its binary logic](image-2.png "Figure 1 :")
2![Figure 2 : QCA Wire](image-3.png "Figure 2 :")
3![Figure 3 : 2-input AND & 2-input OR gatesThe QCA cells can form the primitive logic gates shown in Figure4(inverter gate).](image-4.png "Figure 3 :")
4![Figure 4 : inverter gate](image-5.png "Figure 4 :")
![Design of BCD to Excess-3 Code Converter in Quantum Dots Cellular Automata (QCA) Global Journal of Researches in Engineering ( ) F Volume XIV Issue IV Version Ipolarity of 0, the 3-input majority gate functions as an AND gate. In the example AND gate on the left side of Figure3., out = ab. Similarly, replacing input c with a cell having a fixed polarity of 1 creates a 2-input OR gate. In the example OR gate on the right side of Figure3, out = a+b.](image-6.png "Novel")
![, performs the Boolean function Z= D', Y= CD+(C+D)', X= B' (C+D) + B(C+D)', W= A + B(C+D);](image-7.png "")
5![Figure 5 : QCA Block Diagram of BCD-to-excess-3 code converter](image-8.png "Figure 5 :")
![Figure 7 shows the simulation results of a BCD-to-excess-3 code converter gate. In the Figure, from the input signals of A, B, C and D to the output signals of Z=D', Y=CD+(C+D)', X= B'(C+D)+ B(C+D)', W= A+B(C+D) in this module goes through four clock zones; it means its delay is a full clock cycle. Therefore at the output of Z, Y, X and W are available one clock cycles after A, B , C and has been applied. On the other hand, we can consider the value of the curve shown in Figure 7. Global Journal of Researches in Engineering ( ) F Volume XIV Issue IV Version I (C,D,0),1,Maj(C,D,1)'] = Maj[Maj(0,0,0),1,Maj(0,0,1)'] =Maj[0,1,(0)'] =Maj[0,1,1] =1 X= B' (C+D) + B(C+D)' =Maj[Maj{B' ,0,Maj(C,1,D),}1, Maj{B,0,Maj(C,1,D)'}] = Maj[Maj{(0)' ,0,Maj(0,1,0),}1,Maj{0,0,Maj(0,1,0)'}] =Maj[Maj{1,0,0},1,Maj{0,0,(0)'}]](image-9.png "")

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			Year 2014 © 2014 Global Journals Inc. (US)
			© 2014 Global Journals Inc. (US) Novel Design of BCD to Excess-3 Code Converter in Quantum Dots Cellular Automata (QCA)
			Year 2014 © 2014 Global Journals Inc. (US) Y= CD+(C+D)'
		
		
			

				


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		C+D) + B(C+D)' =Maj[Maj{B
		
			X= B'
		
		
			0,Maj(C,1,D),}1, Maj{B,0,Maj(C,1,D
		
	




* 
	
		
		
			=Maj
		
		
	
	Maj{(0)' ,0,Maj(0,1,1),}1,Maj{0,0,Maj(0,1,1)'}] =Maj[Maj{1,0,1},1,Maj{0,0,(1)'}




* 
	
		
		
			W= A + B
		
		
	
	C+D) =Maj[A,1,Maj{B,0,Maj(C,1,D)}




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