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\title{Investigation the Impact of Silicon Film Thickness on FDSOI and PDSOI MOSFET Characteristics}
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             \author[1]{Towhid Adnan  Chowdhury}

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\date{\small \em Received: 1 January 1970 Accepted: 1 January 1970 Published: 1 January 1970}

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\begin{abstract}
        


The performance of chip is degraded because of the short-channel effect (SCE) as the metal oxide semiconductor field effect transistor (MOSFET) size scales down. Silicon on insulator (SOI) technology helps to reduce the short channel effects and permits a good solution to the miniaturization. The electrical characteristics of fully depleted SOI (FDSOI) and partially depleted SOI (PDSOI) n-channel MOSFET (N-MOSFET) are investigated as silicon film thickness is varied in this paper. Both transistors are compared in terms of electrical parameters which are the threshold voltage, subthreshold slope, on-state current, leakage current and drain induced barrier lowering (DIBL). Silvaco TCAD tools are used for simulating both PDSOI and FDSOI MOSFETs. FDSOI MOSFET is superior to PDSOI MOSFET based on found simulation results.

\end{abstract}


\keywords{silicon on insulator, subthreshold slope, leakage current, threshold voltage, drain induced barrier lowering.}

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\textcolor{GJBlue}{\footnotesize \\ Artificial Intelligence formulated this projection for compatibility purposes from the original article published at Global Journals. However, this technology is currently in beta. \emph{Therefore, kindly ignore odd layouts, missed formulae, text, tables, or figures.}}
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\begin{textblock*}{10cm}(1.05cm,3cm)
{{\textit{CrossRef DOI of original article:}} \underline{}}
\end{textblock*}\let\tabcellsep& 	 	 		 
\section[{I. Introduction}]{I. Introduction}\par
oday devices of minimized area, reduction in power and increased performance have a great demand in the industry of microelectronics. The feasible technique of semiconductor industry to enhance productivity and performances is scaling of device \hyperref[b0]{[1]}. The size of MOSFET has continually been scaled down \hyperref[b1]{[2]}. The submicron technologies have created electrical operational challenges such as threshold voltage (Vth), sub threshold slope and leakage current due to the shrinking of the devices dimensions in MOSFET. The industry is facing difficulty to fulfill the Moore's Law using bulk devices which cause threshold voltage to decrease and leakage current to increase as length of channel decreases because of short channel effect (SCE). Silicon on Insulator (SOI) is considered as a potential alternative over conventional bulk MOSFET due to decreased silicon geometries and simple fabrication process. Radiation hardness, improved switching speeds, reduced leakage currents, better isolation, eliminization of latch up and decrease in the short channel effects are some of the advantages of the SOI devices \hyperref[b2]{[3]}. It has the intrinsic benefit of reduced source and drain areas and reduction of junction capacitance which makes these devices a potential candidate for low power and voltage applications \hyperref[b3]{[4]}\hyperref[b4]{[5]}\hyperref[b5]{[6]}. SOI has several benefits over other technological solution such as no latch up, lower threshold voltage and better sub threshold slope \hyperref[b6]{[7]}\hyperref[b7]{[8]}. There are two types of SOI, which are partially depleted (PD) and fully depleted (FD) depending on the thickness of the silicon film on the insulator. Usually, the thickness of silicon film is between 100nm to 500 nm for PD SOI device. For fully-depleted SOI devices, the thickness of silicon film is about less than 100nm. Due to removal of the floating body effect, FDSOI provides better short channel behaviour compared to the PDSOI. Hui et al. investigated impact of silicon film thickness on leakage current and threshold voltage in PDSOI and FDSOI \hyperref[b9]{[9]}. This paper presents investigation between partially depleted and fully depleted SOI devices in terms of electrical parameters which are threshold voltage, subthreshold slope, on-state current, leakage current and drain induced barrier lowering. TCAD Silvaco software was used for simulation study of SOI devices. Simulation results revealed that the electrical characteristics such as threshold voltage, subthreshold slope and leakage current of fully depleted SOI outperformed than that of partially depleted SOI devices. There is difference in turn on voltage in fully depleted SOI (FDSOI) MOSFET. The threshold voltage is stable in partially depleted SOI (PDSOI) device due to thicker silicon film layer. 
\section[{II. Methodology}]{II. Methodology}\par
To study the electrical parameters on SOI MOSFET a schematic cross-sectional view of the SOI MOSFET, shown in figure \hyperref[fig_0]{1}, is simulated using Silvaco TCAD device simulator. The channel doping concentration is kept at 1×10 17 cm -3 . The source/drain region doping concentration is kept at 1×10 20 cm -3 . Gate length of the device is 1 ?m. Gate oxide (SiO 2 ) thickness and buried oxide thickness are 18 nm and 0.4 ?m respectively. The total device length including drain, channel and source is 3 ?m. Shockley-Read-Hall recombination, field-dependent mobility model and T impact ionization model from Selberherr \hyperref[b10]{[10]} was used for the simulation. Newton methods is used as numeric methods for simulation.  
\section[{III. Results and Discussion}]{III. Results and Discussion}\par
The n-channel PDSOI and FDSOI MOSFET has been investigated in terms of electrical parameters by simulation results obtained using Silvaco TCAD simulation software. Atlas syntax is used to create SOI structures and TonyPlot is used to display simulation results.\par
The impact of silicon film thickness on SOI MOSFET's electrical parameters are shown in table \hyperref[tab_0]{1}. FDSOI MOSFET has thickness of silicon film below 0.1 ?m while for PDSOI it is greater than 0.15 ?m for the simulated structure \hyperref[b11]{[11]}. The gate to source voltage needed to turn on the MOSFET is defined as threshold voltage, V th \hyperref[b7]{[8]}. Smaller threshold voltage satisfies high performance of device with technology scaling \hyperref[b12]{[12]}. The threshold voltage for PDSOI is above 0.68 V and for FDSOI below 0.47 V as extracted from simulation results and also shown in figure \hyperref[fig_2]{2}. So the turn on voltage of PDSOI is larger than FDSOI from the results. This is the reason for FDSOI devices consuming less power and gaining higher speed.    A high on-state current(I on ) is needed to increase the driving force of the device. From figure \hyperref[fig_5]{5}, it can be said that the on-state current is greater when thickness of silicon film is reduced. As threshold voltage is increased, the leakage current(I off ) is decreased \hyperref[b14]{[14]}. It can be decided that in PDSOI the leakage current is lesser but the variation is insignificant as shown in figure \hyperref[fig_6]{6}. Static power dissipation is created by leakage current when the device is not powered \hyperref[b15]{[15]}. Static power dissipation will be small if leakage current is smaller. Thus, from the simulation results the static power dissipation of PDSOI will be smaller compared to FDSOI.  It is concluded that with increase of thickness of silicon film, the threshold voltage and subthreshold slope increased on SOI MOSFET which allows a smaller operating voltages and a higher switching speed for FDSOI. PDSOI can ensure a low static power dissipation as leakage current is small. But the leakage currents are in pA (10 -12 ) range for both SOIs. The DIBL parameter value shows that FDSOI is less sensitive to short channel effects. Based on the results obtained, FDSOI MOSFET displays superior performance compared to PDSOI MOSFET because of its lesser threshold voltage, steeper subthreshold slope, high on-state current and improved DIBL value in the device. 
\section[{Global Journal of Researches in Engineering}]{Global Journal of Researches in Engineering}\begin{figure}[htbp]
\noindent\textbf{1}\includegraphics[]{image-2.png}
\caption{\label{fig_0}Figure 1 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{}\includegraphics[]{image-3.png}
\caption{\label{fig_1}}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{2}\includegraphics[]{image-4.png}
\caption{\label{fig_2}Figure 2 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{3}\includegraphics[]{image-5.png}
\caption{\label{fig_3}Figure 3 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{4}\includegraphics[]{image-6.png}
\caption{\label{fig_4}Figure 4 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{5}\includegraphics[]{image-7.png}
\caption{\label{fig_5}Figure 5 :FD}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{6}\includegraphics[]{image-8.png}
\caption{\label{fig_6}Figure 6 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{7}\includegraphics[]{image-9.png}
\caption{\label{fig_7}Figure 7 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{1} \par 
\begin{longtable}{P{0.12172839506172839\textwidth}P{0.1511111111111111\textwidth}P{0.13641975308641974\textwidth}P{0.1385185185185185\textwidth}P{0.18259259259259258\textwidth}P{0.11962962962962963\textwidth}}
Silicon Film Thickness(?m)\tabcellsep Threshold Voltage,Vth(V)\tabcellsep Subthreshold slope(mV/dec)\tabcellsep On-state current,I on (?A)\tabcellsep Leakage current,I off (pA)\tabcellsep DIBL(mV/V)\\
0.07\tabcellsep 0.3206\tabcellsep 65.45\tabcellsep 81.89\tabcellsep 12.42\tabcellsep 74.84\\
0.09\tabcellsep 0.4686\tabcellsep 67.15\tabcellsep 68.12\tabcellsep 0.415723\tabcellsep 113.34\\
0.11\tabcellsep 0.6081\tabcellsep 86.75\tabcellsep 55.56\tabcellsep 0.301249\tabcellsep 166.66\\
0.13\tabcellsep 0.6731\tabcellsep 94.5\tabcellsep 46.16\tabcellsep 0.241121\tabcellsep 178.18\\
0.15\tabcellsep 0.6846\tabcellsep 95.92\tabcellsep 42.69\tabcellsep 0.194797\tabcellsep 180.73\\
0.20\tabcellsep 0.6869\tabcellsep 96.26\tabcellsep 41.53\tabcellsep 0.288933\tabcellsep 179.56\\
0.25\tabcellsep 0.6863\tabcellsep 96.27\tabcellsep 41.27\tabcellsep 0.347851\tabcellsep 177.83\\
0.30\tabcellsep 0.6902\tabcellsep 96.74\tabcellsep 40.35\tabcellsep 0.284068\tabcellsep 175.69\end{longtable} \par
 
\caption{\label{tab_0}Table 1 :}\end{figure}
 		 		\backmatter  			 
\subsection[{Conflict of Interest}]{Conflict of Interest}\par
The author declares that there is no conflict of interest.			 			  				\begin{bibitemlist}{1}
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\end{document}
