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\textcolor{GJMediumGrey}{\rule{\textwidth}{2pt}} \vskip16pt \textcolor{GJBlue}{\large\bfseries\abstractname\space} }{% \vskip8pt \textcolor{GJMediumGrey}{\rule{\textwidth}{2pt}} \vskip16pt } \usepackage[absolute,overlay]{textpos} \makeatother \usepackage{lineno} \linenumbers \begin{document} \author[1]{r ravindraiah} \author[2]{C.K.Hemantha Lakshmi} \author[3]{C.K.Hemantha Lakshmi} \affil[1]{ Dept., of ECE, MITS, Madanapalle, Andhra Pradesh} \renewcommand\Authands{ and } \date{\small \em Received: 11 February 2012 Accepted: 29 February 2012 Published: 15 March 2012} \maketitle \begin{abstract} To meet modern complex control systems communication demands, my paper presents a multi channel UART controller based on FIFO (first in first out) and FPGA (field programmable gate array).The paper presents design method of asynchronous FIFO and structure of controller.This controller is designed with FIFO circuit block and UART (universal asynchronous teceiver transmitter) circuit block with in FPGA to implement communication in modern complex control systems quickly and effectively. This controller can be used to implement communication when master equipment and slaver equipment are set at different baud rate. It can also be used to reduce synchronization error between sub systems in asystem with several sub systems. The controller is reconfigurable and scalable. The whole scenario is simulated using VHDL coding. \end{abstract} \keywords{communication, complex, programmable, synchronization.} \begin{textblock*}{18cm}(1cm,1cm) % {block width} (coords) \textcolor{GJBlue}{\LARGE Global Journals \LaTeX\ JournalKaleidoscope\texttrademark} \end{textblock*} \begin{textblock*}{18cm}(1.4cm,1.5cm) % {block width} (coords) \textcolor{GJBlue}{\footnotesize \\ Artificial Intelligence formulated this projection for compatibility purposes from the original article published at Global Journals. However, this technology is currently in beta. \emph{Therefore, kindly ignore odd layouts, missed formulae, text, tables, or figures.}} \end{textblock*} \let\tabcellsep& \section[{Introduction}]{Introduction}\par oday, owing to availability of state-of-the-art microcontrollers and digital signal processors(DSPs), complex control algorithms can be easily implemented to attain the desired system performance \hyperref[b2]{[3]}.But in actual control systems it is difficult to attain the expected result for various factors affect the control systems such as control algorithms itself, capability of implement equipment and states of control circumstance. Except those factors, communication parameters of control systems including baud rate, BER (bit error rate) and synchronization between sub systems also engender great effect .In order to improve precision of control system and make good use of modern control algorithms ,we should pay much more attention on communication in control systems \hyperref[b0]{[1]}.\par In several control systems, UART a kind of serial communication circuit used widely. A universal asynchronous receive transmit is an integrated circuit which plays most important role in serial communication. It handles the conversion between serial and parallel data. Serial communication reduces the distortion of a signal therefore makes data transfer between two systems separated in great distance possible \hyperref[b1]{[2]}.\par In some complex systems, communications between the master controller and slaver controllers are implemented by serial or parallel port. Parallel communication needs a lot of multi-bit address bus and data bus and it is only convenient for short distance transmission. Serial communication is another way of communication used extensively because of its simple structure and long transmission distance .But sometimes a common serial port could not meet requirements of complex systems with different baud rates equipments even some special baud rate equipments. It is impossible to implement this multi baud rate communication system without a special baud rate converter \hyperref[b2]{[3]}. A RAM array with separate read and write ports is used to store data .The writer pointer points to the location that will be written next, and read pointer points to the location that will be read currently. A write operation increments the writer pointer and read operation increments the read pointer. On reset, both pointers are rest to zero, the FIFO is empty. The write pointer happens to be the next FIFO location to be written and read pointer is pointing to invalid data. The responsibility of status block is to generate the EMPTY and FULL signals to the FIFO \hyperref[b3]{[4]}. If the FULL signal is active then the FIFO cannot accommodate more data and if the EMPTY is active then the FIFO cannot provide more data to read out. When writing data into the FIFO "wclk"will be used as the clock domain and when reading data out of the FIFO "rclk" will be used as the clock domain. These both clock domains are asynchronous. \section[{c) Factors for the design of Asynchronous FIFO}]{c) Factors for the design of Asynchronous FIFO}\par In the designing of asynchronous FIFOs, two important factors are considered. One is how to judge FIFOs status according to the writer pointer and read pointer. The other is how to design circuit to synchronize asynchronous clock domains to avoid metastability. We can use software codes in VHDL to design FPGAs hardware structure, it is easy to create and adjust to satisfy requirements of applications. There are one UART used to communicate with PC or other main MCU and there are also four other UARTs used to communication with sub MCUs \hyperref[b4]{[5]}. Each channel has two FIFOs one for receiving data and the other for transmitting data. Each FIFO"s depth is 64 bytes. The software flow chart is shown in figure \hyperref[fig_6]{6}. As shown in figure ,when FIFO is full we cannot write any more byte into the FIFO.At this time, the status detector will set CS high to indicate that the FIFO is full and when FIFO is full you cannot write any more byte into the FIFO. At this time, the status detector will set CS high to indicate that the FIFO is full and stop writing to the FIFO. When FIFO is empty we cannot read from it any more. Then the status detector will set empty high to indicate the status of FIFO and stop reading from it \hyperref[b5]{[6]} \hyperref[b6]{[7]}.\par When FIFO is not full or empty it will be written or read data according to the control order. After finishing all write or read operation it will stop until next access is coming. \section[{III.}]{III.} \section[{Simulation Results}]{Simulation Results} \section[{a) Simulation And Verification}]{a) Simulation And Verification}\par To verify design of the controller a test bench is written to make verification in modelsim .Data received from the PC or other main MCU will be stored in FIFO"s within FPGA till the controller will set a kind of baud rate according to commands desired. The controller is receiving data and store the data received to different FIFO waiting for read. When sub-controllers are required to receive data at different baud rates, the controller can set each channel at its required baud rate to transmit data. The controller sends data at the same time but at different baud rate. IV. \section[{Conclusion}]{Conclusion}\par This paper introduces a method to design a method to design a asynchronous FIFO based on FPGA. And using asynchronous FIFO technique implements a multi channel UART controller within FPGA based on SRAM wit high speed and reliability .The controller can be used to implement communications in complex system with different baud rates of sub controllers. And it also can be used to reduce time delays between sub controllers of a complex control system to improve the synchronization of each sub controller. The controller is reconfigurable, so the controller"s fault is that it would be influenced by the radiation from surroundings and by short time pulses easily.\begin{figure}[htbp] \noindent\textbf{}\includegraphics[]{image-2.png} \caption{\label{fig_0}}\end{figure} \begin{figure}[htbp] \noindent\textbf{1}\includegraphics[]{image-3.png} \caption{\label{fig_1}Figure 1 :}\end{figure} \begin{figure}[htbp] \noindent\textbf{}\includegraphics[]{image-4.png} \caption{\label{fig_2}}\end{figure} \begin{figure}[htbp] \noindent\textbf{34}\includegraphics[]{image-5.png} \caption{\label{fig_3}Figure 3 :Figure 4 :}\end{figure} \begin{figure}[htbp] \noindent\textbf{5}\includegraphics[]{image-6.png} \caption{\label{fig_5}Figure 5 :}\end{figure} \begin{figure}[htbp] \noindent\textbf{6}\includegraphics[]{image-7.png} \caption{\label{fig_6}Figure 6 :}\end{figure} \begin{figure}[htbp] \noindent\textbf{7}\includegraphics[]{image-8.png} \caption{\label{fig_7}Figure 7 :}\end{figure} \begin{figure}[htbp] \noindent\textbf{8}\includegraphics[]{image-9.png} \caption{\label{fig_8}Figure 8 :}\end{figure} \footnote{F © 2012 Global Journals Inc. (US)2012JulyAuthor ? : Assistant Professor, Dept., of ECE, MITS, Madanapalle, Andhra Pradesh. E-mail : hemanthaster@gmail.com Author ? : Assistant Professor, Dept., of CSE, KEC, Kuppam, Andhra Pradesh. Email : ckhemantha@gmail.com Author ? : M.Tech, Dept of EEE., NIT Nagpur, Email : ckmahesh111@gmail.com} \footnote{© 2012 Global Journals Inc. (US)2012July different, it means that the write pointer has wrapped one more time that the read pointer. If the MSBs of the two pointers are the same, it means that both pointers have wrapped the same number of times.} \footnote{F © 2012 Global Journals Inc. (US) 2012 July} \footnote{© 2012 Global Journals Inc. (US)} \footnote{© 2012 Global Journals Inc. (US) 2012 July} \backmatter \begin{bibitemlist}{1} \bibitem[Jayram Bhaskar and Primer]{b5}\label{b5} \textit{}, "a Vhdl Jayram Bhaskar , Primer . Prentice Hall Publications. (2nd edition) \bibitem[Stallings]{b2}\label{b2} \textit{Data and Computer communications}, William Stallings . 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