@incollection{, 3B7C3E9ADED479CDFF1871CDF063E7EF , author={{rravindraiah} and {C.K.HemanthaLakshmi} and {C.K.HemanthaLakshmi} and {Dept., of ECE, MITS, Madanapalle, Andhra Pradesh}}, journal={{Global Journal of Researches in Engineering}}, journal={{GJRE}}2249-45960975-586110.34257/gjre, address={Cambridge, United States}, publisher={Global Journals Organisation}1272126 } @incollection{b0, , title={{UART -Based reliable Communication and performance analysis}} , author={{ LKHu } and { QWang }} , journal={{Computer Engineering}} 32 10 , year={May 2006} } @incollection{b1, , title={{Implementation of Parallel Signal processing system based on FPGA and multi-DSP}} , author={{ FSPan } and { FZhao } and { JXi } and { YLuo }} , journal={{Computer Engineering}} 32 23 , year={Dec 2006} } @book{b2, , title={{Data and Computer communications}} , author={{ WilliamStallings }} , publisher={McGraw-Hill publications} } @book{b3, , title={{Fundamentals of Digital Logic with VHDL Design}} , author={{ StephenBrown } and { ZvonkoVranesic }} , year={July 2004} , publisher={McGraw-Hill, Hardcover, Published} , note={2nd edition} } @book{b4, , author={{ CharlesHRoth }} , title={{Digital system design using VHDL}} , note={2nd edition, Thomson publication} } @book{b5, , title={{}} , author={{ "a VhdlJayram Bhaskar } and { Primer }} , publisher={Prentice Hall Publications} , note={2nd edition} } @book{b6, , title={{VHDL Analysis and Modeling of Digital systems}} , author={{ ZainalabedinNawabi }} , year={January 1998} , publisher={Hardcover} , note={2nd edition. Published} } @incollection{b7, , title={{Design of interface Between High speed A/D and DSP based on FIFO}} , author={{ XDWu } and { BDai }} , journal={{Journal of Beijing Institute of petrochemical Technology}} 14 12 , year={June 2006} }