he adder is one of the most critical components of a central processing unit. The object of the adders not only adding of bits but also involves in address calculation, subtraction, division and multiplication, the adders are critical components to determine the speed, delay and power of the overall system, low power adders are always preferable. Due to the popularity of portable electronic products low power system has attracted more attention in recent years, an system on chip (SOC) design can contain more and more components that lead to a higher power density. This makes power dissipation reach the limits of what packaging, cooling or other infrastructure can support, reducing the power consumption not only can enhance battery life but also can avoid the overheating problem which would increase the difficulty of packaging or cooling. Therefore the consideration of power consumption in complex SOCs has become a big challenge to designers, moreover in modern VLSI designs [3][4][5].

Lowering power is one of the greatest challenges facing the IC industry Today, temperature profile and battery life requirements for tethered and un tethered systems have made power consumption a primary optimization target for IC industry [2]. IC power consumption consists of three basics components: switching power, short circuit power and leakage power [6][7].

Dynamic power

Dynamic power is square of supply voltage, therefore by reducing supply voltage we can reduce dynamic power [8].

The leakage power is mainly due to sub threshold current and it may be defined as the drain to source current of the transistor operating in the weak inversion region of MOSFET this subthreshold leakage may be defined as in eq (2) give s a simple method for estimating the leakage current in a single NMOS transistor [9][10][11].

( )

V t is the thermal voltage and is given by Q/KT and n is the sub threshold slope coefficient. Generally there are varies leakage reduction techniques based on mode of operation of systems the two operation modes are active mode and stand by mode or idle mode. Most of the leakage power reduction techniques will be based on idle mode [12]. SECTION2: gives an overview of the Novel PMOS and NMOS and their simulation results, SECTION3 presents Novel 3 bit full adder and conventional full adder, SECTION 4 describes experimental results of conventional, Novel full adders and DTMOS full adders, SECTION5gives conclusions.

II.

Ultra low power operation plays a major role in designing of CMOS circuits in subthreshold regime, for any digital or analog design the basic components are PMOS and NMOS devices, the power consumption of this basic elements determine the overall power of the system. In this section we provide Novel PMOS and NMOS, simulations have been carried out in cadence design frame work to verify the functionality of the

The 28 transistor full adder is the pioneer traditional adder circuit, the schematic of this adder is shown. This adder cell is built using equal number of NFET and PFET transistors, the MOS logic can be realized using equations [1].

The conventional full adder consumes more power compared to Novel full adder, both conventional and Novel full adders are simulated and their average power is calculated [14].

An investigation has been carried out for calculating average power, static power of conventional full adder and the Novel full adder and compared their powers at 45nm technology using virtuoso design environment.

A novel CMOS adder may have an overhead area, but it consumes less power [15].

The performance of many large circuits are strongly dependent on the performance of the full adder circuits that have been used. An attempt has been made to design 84T novel full adder with low power consumption. In this paper we have simulated conventional full adder and Novel full adder and calculated average power. As mentioned earlier as the technology advances apart of dynamic power, there will be a equal part of leakage power, therefore a Novel full adder will suitable for low power design.