ccording to the ITRS 2015,Now a days the memory area is increasing than logic area in SOCs.Fig. 1 [1] shows that shrinking the technologies give rise to defect and new fault models.Thus, the new trends in Multiported memory testing will be driven by the following items. BIST: The new fault and new defects eliminate using BIST. The only solution that allows at-speed testing for embedded memories, it has generate fault detection and coverage, the higher repair efficiency only detecting the faults is no longer sufficient for SOCs so memory repair is also necessary for this purpose both diagnosis and repair algorithm are required. BISR: Combining BIST with efficient and low cost repair schemes in order to improve the yield and system reliability as well.
Fig. 1 : Embedded Memories in Future SOCs [1] Auhtor ? ?: Department of Electronics and telecommunication Bharati Vidyapeeth's College of Engineering for Women Pune, 43 Savitribai Phule Pune University. e-mails: [email protected], [email protected] There are two methods which are efficiently used. These methods are as follow:
Dr. R.K. Sharma et al. [2] introduced Redundancy Array Logic and BISR mechanism used to low cost repair the fault and to improve the system reliability.
Bo-Cheng Charles Lai et al. [4] introduced designs of multiported memories that leverage BRAMs have been proposed to attain better utilization of FPGA resources as well as system performance. BRAMs in an FPGA can support two access ports that can be used as either a read or a write port.
Global Journal of Researches in Engineering ( ) Volume XVII Issue II Version I Yash Jyothi et al. [1] introduced Asynchronous P-MBIST method for fault detection and repair of multiported memory. The main advantage is to get power efficient P-MBIST, it is being proposed to use handshaking signals instead of using clock and implemented on FPGA. Clocks are used to synchronize the test blocks on chip and handshaking signals are used to communicate between blocks of test controller.
Memory Built-In Self Test is test circuitry used to test on-chip memory devices. It contains finite state machine to generate test vectors to test vectors to test memory during test mode. Test coller includes Address, Data, read/write control. This address, data and read/write control signal is given as input to comparator and multiplexer. Multiplexer uses two modes of operations: Normal mode-In normal mode memory acts as a normal memory. Test Mode-During test mode test coller provides data and address to memory for testing purpose. In test mode while performing read operation data from test coller and output of memory are given to comparator for fault detection. Then, comparator compares test vectors with memory output. If, memory is working properly then, No Fault is detected and it is declared as memory is fault free but, if fault pulse becomes high it shows that memory under test is faulty.
The block diagram shown in Fig. 3 I. [1] Table No.1: Microcode Instruction [1] V.
The flow of asynchronous P-MBIST is as shown in fig . 4, fig. 5
The simulation of asynchronous P-MBIST is depending upon request signal and mode. Output Response: Normal Mode: When mode=0, MUX selects normal mode, then test controller is off so as comparator is off. At this moment memory acts as normal memory without under test and generates external address and data if rw=0(i.e. reads address and corresponding data).During this mode as comparator is off, no fault pulse is generated. In this mode, memoutdata (memory output) data is data (External data) provided for normal memory operation. Test Mode: If mode=1, Memory is under test. If req=1, microcode instruction storage generates Read/Write control for test collar. Test collar writes data if tcrw=0 otherwise read to memory through MUX. The data from test collar and output of memory is compared in comparator. If mismatch happens at output of comparator, comparator generates fault pulse=1 otherwise fault pulse=0 [1]. During the normal mode each incoming address is compared with the address field of programmed redundant words. If there is a match, the data field of the redundant word is used along with the faulty memory location for reading and writing data. The output multiplexer of Redundant Array Logic then ensures that in case of a match, the redundant word data field is selected over the data read out ( = 0) of the faulty location in case of a read signal. This can be easily understood by the redundancy word detail shown in Figure 7. VII. Results
The single port memory support single read and write operation.
Year 2017 | |||
22 | |||
II Version I | Data | R/W signal | |
( ) Volume XVII Issue | MBIST Controller | Input MUX Multiported | |
Journal of Researches in Engineering | Redundancy circuit | Memory Output MUX Data Out | |
Global |
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