Simulation and Analysis of Power Quality Improvement using Multilevel Unified Power Quality Conditioner

Table of contents

1. I. Introduction

he increased use of non-linear loads deteriorate power system voltage and current waveforms as they inject harmonics into the system. This results in increased losses, lower efficiency, failure of equipment etc. in the power system. Apart from voltage and current harmonics, voltage sag, voltage swell, voltage outage also can lead to poor quality of power [1]. Harmonic compensation and voltage regulation have become more important as imbalance in the voltage and presence of harmonics have been serious issues. Hence, there is a great need to mitigate these power quality issues.

The introduction of advanced power electronics technology has led to the development of active power filters which are viable solution to these power quality problems [1,2].

The general arrangement of Unified power quality conditioner is shown in Fig. 1. The main function of a UPQC is to compensate voltage and current harmonics.

The UPQC combines series and shunt active filters with a common dc link. The series active filter suppresses voltage distortions while the shunt filter Author ?: e-mail: [email protected] cancels current distortions such that this combination allows simultaneous compensation of voltages and currents supplied to the sensitive load to see that they are sinusoidal and balanced. Fig. 1 : General configuration of UPQC Multilevel inverters play an important role in the reduction of harmonic content in the voltages and currents. The multilevel inverters can synthesize high output voltage from smaller voltage levels and thus the current ripples and voltage harmonics are reduced. The UPQC presented in this work consists of three level converter topology [3,4]. The performance of UPQC can be optimized because of reduction in the size of passive components and transformers [4].

2. II. The Upqc Controller

The UPQC controller is composed of PLL circuit, Reference Voltage Algorithm and Reference Current Algorithm [4,5,6].

The PLL circuit has the system voltages Vab and Vcb i.e (Vab =Vas -Vbs, Vcb = Vcs -Vbs) as inputs and the outputs are the signals Pll_a, Pll_b and Pll_c as shown in Fig. 2.

3. Fig. 2 : The synchronizing ciruit

The PLL circuit guarantees the load voltages and source currents to be balanced sinusoidal waveforms at fundamental frequency.

The reference current control strategy is shown in Fig. 3. The reference currents algorithm control block determines six reference currents (i aref1, i bref1, i cref1 ) and (i aref2 ,i bref2 ,i cref2 ) by using the outputs of PLL (Pll-a,Pll-b,Pllc) , the DC link voltages (V dc1 ,V dc2 ) and the load currents (I al, I bl ,I cl ) as inputs. The shunt active power filter will then synthesize the reference currents. The "reference voltage algorithm" shown in Fig. 4 calculates, the reference voltages (V aref , V bref , V cref ) by using system input voltages (V as , V bs , V cs ) and PLL outputs(pll-a, pll-b, pll-c) that will be synthesized by the series power converter.

Note: .

4. III. Switching Strategy of Three Level Converters

In order to illustrate the switching control technique applied to the series and shunt active power converters, a basic three level NPC (Neutral Point Clamped ) topology as shown in Fig. 5 is used [7,8].

5. Fig. 5 : Three level Neutral point clamped converter

Each leg has four switching devices connected in series. As an example, phase "a" is considered to explain the behavior of the circuit.

The output of the inverter can take three voltage levels based on the switching states of the devices. The output Va is positive when switches S1a and S2a are ON, it is negative when S3a and S4a are turned ON, and it is '0' when switches S2a and S3a are ON. The switching states of the devices and the corresponding output voltages with respect to the dc mid-point are indicated in the following Table I.

The switching strategy of the series active filter is shown in Fig 6 . In this technique, the reference signal is compared with measured signal, the error is amplified and processed by PWM generator to obtain Va_PWM. This signal is compared with two triangular waves of different limits having unit magnitude. The switching control strategy of the shunt active converter is shown in In this work, Phase Disposition multicarrier scheme is applied to Sinusoidal PWM. In this modulation, the reference sine wave is compared with the level shifted carrier triangular waves for producing the pulses. For a three level inverter, two triangular carrier waves of same frequency and amplitude are compared with the reference wave. The plane is divided into 6 triangular major sectors numbered I to VI each of 60 0 of fundamental cycle. There are 4 minor sectors within each major sector such that 24 minor sectors are there in the plane.

The vertices of these minor sectors represent the voltage vectors. In the above plane, V0 is the zero voltage vector, large voltage vectors are represented by V13, V14, V15, V16, V17, V18 and V7, V8, V9, V10, V11, V12 are the medium voltage vectors. To determine the location of the command vector V* in a given major sector, first space vector phase angle' ?' is calculated and then sector is determined. The determination of major sector is done as follows:

Table I : Determination of major sector

6. Range of '? '

Major sector number

0 ? ? < 60 0 I 60 ? ? < 120 0 II 120 ? ? < 180 0 III 180 ? ? < 240 0 IV 240 ? ? < 300 0 V 300 ? ? < 360 0 VI

Let us consider space vector diagram of sector I as shown in Fig . 9. It contains 4 minor triangles D1, D7, D13 and D14. The reference vector can be located in any of these 4 regions, where each region is limited by three adjacent vectors.

If the triangular sector where the command vector lies is defined by vectors Vx, Vy, and Vz assuming their durations Tx, Ty, and Tz respectively and Tx + Ty + Tz = Ts ,then V*= Vref can be synthesized by Vx, Vy, and Vz as follows : (?/6<?<?/3), V* lies in sector D14 and can be synthesized by Vectors V2. V7, and V14. X, Y, and Z can be determined as follows:

X = 2m [cos (?) - ?????? ? ?3 ] Y = -1 + m 4 ?????? ? ?3 Z = 2-2m [cos (?) + ?????? ? ?3 ]

Similar argument can be applied ,when the reference vector lies in the others major sectors. The above calculations for the entire coordinate plane can be obtained by replacing ? by ? -60 0 , ? -120 0 , ? -180 0 , ? -240 0 , and ? -300 0 respectively.

7. V.

8. Simulation Results

Simulations were carried out in MATLAB/ SIMULINK on three-level Neutral Point Clamped Unified Power Quality Conditioner connected to a non-linear load employing Sinusoidal Pulse Width Modulation and Space Vector Pulse Width Modulation techniques and the results are presented below. FFT analysis is carried out in order to measure %THD in the load voltage and source current.

To study the performance of the UPQC, 5 th and 7 th harmonics are deliberately injected into the system and simulations were carried out to show the response of the UPQC. The series inverter is put into operation at 0.2sec and shunt inverter at 0.5sec.FFT analysis is carried out on the load voltage at 0.1sec and the THD is found to be 12.32%. In the second analysis, FFT is done at 0.8sec i.e. after connecting UPQC and THD is reduced to 2.01% FFT analysis of source current FFT analysis of source current before connecting UPQC FFT analysis of source current after connecting UPQC FFT analysis is carried out on the source current at 0.1sec before connecting UPQC and the THD is found to be 33.97%. In the second analysis, FFT is done at 0.6sec after connecting UPQC and THD is 2.01% b) Simulation results of 3level UPQC with SVPWM 19, it is clear that the harmonics are reduced to some extent after 0.1 sec where series filter is switched ON and from 0.25sec onwards there is a considerable reduction in the harmonics as both filters are in operation.

9. FFT analysis of load voltage

FFT analysis of load voltage before connecting UPQC FFT analysis of load voltage after connecting UPQC FFT analysis is carried out on the load voltage at 0.05sec before switching ON series and shunt inverters and the THD is found to be 12.32%. FFT analysis of load voltage again carried out at 0.3sec after connecting both series and shunt filters and THD is found to be 1.27%.

Figure 1. Fig. 3 :
3Fig. 3 : Reference current algorithm control strategy
Figure 2. Fig. 4 :
4Fig. 4 : Reference voltage algorithm control strategy
Figure 3.
Fig 7. This strategy compares the two reference signals Iaref1 and Iaref2 with measured currents, the errors are then amplified and processed by PWM generator to produce I a1-pwm and I a2-pwm. These signals are compared with two triangular trigger waves of different limits having unit magnitude.
Figure 4. Fig. 6 :
6Fig. 6 : Series switching control strategy
Figure 5.
b) Space Vector Pulse Width Modulation ii Space Vector diagram of 3-level SVPWM inverterThe space vector diagram of 3-level inverter is shown in Fig.8[9,0,11].
Figure 6. Fig. 8 :
8Fig.8 : Space vector diagram of three-level inverter
Figure 7. Fig. 9 :Case 1 : 2 X + 1 2 (
9122Fig.9 : Space vector diagram of Sector -I Vref = V* = Vx (Tx/ Ts) + Vy (Ty/ Ts) + Vz (Tz/ Ts) Tx / Ts + Ty/ Ts + Tz/ Ts = 1, Tx / Ts = X , Ty/ Ts = Y and Tz/ Ts = Z Where, T S is the switching period. Based on vector synthesis principle, the following equations can be written. X + Y + Z = 1 , Vx X + Vy Y + Vz Z = V* The equations for the boundaries of modulation ratio Mark l, Mark 2, and Mark 3 can be obtained as follows: Mark 1 =
Figure 8. Fig. 11 :
11Fig.10 : Sourcevoltage
Figure 9. Fig. 13 :
13Fig.13 : Current injected by shunt inverter
Figure 10. Fig. 15 :
15Fig.15 : Sourc Voltage
Figure 11. Fig. 17 :
17Fig.17 : Load voltage after connecting UPQC Fig. 15 shows source voltage with 5 th and 7 th harmonic injection. Fig.16 indicates the voltage injected by the series inverter from 0.1 sec and Fig.17shows the load voltage after compensation.
Figure 12.
Fig.15shows source voltage with 5 th and 7 th harmonic injection. Fig.16indicates the voltage injected by the series inverter from 0.1 sec and Fig.17shows the load voltage after compensation.
Figure 13. Fig. 18 :
18Fig.18 : Current injected by shunt inverter The shunt filter is switched on at 0.25 sec and started injecting current
Figure 14. Fig. 19 :
19Fig.19 : Source current From Fig.19, it is clear that the harmonics are reduced to some extent after 0.1 sec where series filter is switched ON and from 0.25sec onwards there is a considerable reduction in the harmonics as both filters are in operation.
Figure 15. Table . I
.
SWITCHING STATES OUTPUT
VOLTAGE
S1a S2a S3a S4a Va
ON ON OFF OFF +Vdc/2
OFF OFF ON ON -Vdc/2
OFF ON ON OFF 0
1

Appendix A

Appendix A.1

FFT analysis of source current after connecting UPQC FFT analysis is carried out on the source current at 0.07sec before connecting UPQC and the THD is found to be 33.97%. In the second analysis, FFT is done at 0.6sec after connecting UPQC and measured THD is 0.61% The above results are shown in the form of graphs for better understanding

The above table and graphs clearly show that the % THD of both load voltage and source current is less with SVPWM when compared to SPWM and within the prescribed limits of IEEE -519.

Appendix A.2 VI. Conclusion

The performance of three level UPQC has been evaluated using Sinusoidal Pulse Width Modulation and Space Vector Pulse Width Modulation techniques. To prove the effective compensation by UPQC, harmonics are deliberately injected into the source voltage and the UPQC has successfully reduced harmonics from load voltage and source current. The %THD content in the load voltage and source current after compensation is very less and comply with IEEE-519. The simulation results show that the Total Harmonic Distortion of the load voltage after UPQC is put into operation is less in case of SVPWM compared to SPWM.

Appendix B

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  3. Tulasi Ram Das. G Sree Lakshmi Dr , . S Kamakshaiah Dr . Analysis of Two & Three Level Diode Clamped Multilevel Inverter Fed PMSM Drive Using SpaceVector Pulse Width Modulation (SVPWM) "-Proc. of the Second Intl. Conf. on Advances in Computer, Electronics and Electrical Engineering, 2013. p. CEEE.
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  6. Multilevel Inverters : A Survey of Topologies, Controls and Applications. Jose Rodriguez , Sheng Jih , Fang Zheng Lai , Peng . IEEE transactions on Industrial Electronics August'2002. 49 (4) .
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  8. Control Strategies for Series and Shunt Active Filters. M Aredes , F C Luís , Jaime M Monteiro , Miguel . Proc. (CDROM) of the 2003 IEEE Bologna Power Tech -IEEE Bologna Power Tech Conference, ((CDROM) of the 2003 IEEE Bologna Power Tech -IEEE Bologna Power Tech ConferenceBologna, Italy
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Notes
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Date: 2016-01-15